SP6121CN-L Datasheet, PDF(5/42 Page) Sipex Corporation – Low Voltage, Synchronous Step Down PWM Controller

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SP6121CN-L Datasheet, PDF (5/42 Pages) Sipex Corporation – Low Voltage, Synchronous Step Down PWM Controller

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THEORY OF OPERATION

value is selected to match the MOSFET charac-

teristics. When the over-current threshold is

exceeded, the over-current comparator sets the

fault latch and terminates the output pulses. The

controller stops switching and goes through a

hiccup sequence. This prevents excessive power

dissipation in the external power MOSFETs

during an overload condition. An internal delay

circuit prevents that very short and mild over-

load conditions, that could occur during a load

transient, activate the current limit circuit.

A low power sleep mode can be invoked in the

SP6121 by externally forcing the COMP pin

below 0.3V. Quiescent supply current in sleep

mode is typically less than 25ÂµA. An internal

5ÂµA pull-up current at the COMP pin brings the

SP6121 out of shutdown mode.

The SP6121 also includes under-voltage lock-

out and over-voltage protection. Output over-

voltage protection is achieved by turning off the

high side switch, and turning on the low side N-

channel MOSFET full time.

Enable

Low quiescent mode or âSleep Modeâ is initi-

ated by pulling the COMP pin below 0.3V with

an external open-drain or open-collector tran-

sistor. Supply current is reduced to 25ÂµA (typi-

cal) in shutdown. On power-up, assuming that

VCC has exceeded the UVLO start threshold

(2.79V), an internal 5ÂµA pull-up current at the

COMP pin brings the SP6121 out of shutdown

mode and ensures start-up. During normal oper-

ating conditions and in absence of a fault, an

internal clamp prevents the COMP pin from

swinging below 0.6V. This guarantees that dur-

ing mild transient conditions, due either to line

or load variations, the SP6121 does not enter

shutdown unless it is externally activated.

During Sleep Mode, the high side and low side

MOSFETs are turned off and the internal soft

start voltage is held low.

UVLO

Assuming that there is not shutdown condition

present, then the voltage on the VCC pin deter-

mines operation of the SP6121. As VCC rises,

the UVLO block monitors VCC and keeps the

high side and low side MOSFETS off and the

internal SS voltage low until VCC reaches 2.79V.

If no faults are present, the SP6121 will initiate

a soft start when VCC exceeds 2.79V.

Hysteresis (about 100mV) in the UVLO com-

parator provides noise immunity at start-up.

Soft Start

Soft start is required on step-down controllers to

prevent excess inrush current through the power

train during start-up. Typically this is managed

by sourcing a controlled current into a timing

capacitor and then using the voltage across this

capacitor to slowly ramp up either the error amp

reference or the error amp output (COMP). The

control loop creates narrow width driver pulses

while the output voltage is low and allows these

pulses to increase to their steady-state duty

cycle as the output voltage increases to its regu-

lated value. As a result of controlling the induc-

tor volt*second product during startup, inrush

current is also controlled.

In the SP6121 the duration of the soft-start is

controlled by an internal timing circuit that

provides a 0.4V/ms slew-rate, which is used

during start-up and over-current to set the hic-

cup time. The SP6121 implements soft-start by

ramping up the error amplifier reference voltage

providing a controlled slew-rate of the output

voltage, thereby preventing overshoot and in-

rush current at power up.

The presence of the output capacitor creates

extra current draw during startup. Simply stated,

dVOUT/dt requires an average sustained current

in the output capacitor and this current must be

considered while calculating peak inrush cur-

rent and over current thresholds. An approxi-

mate expression to determine the excess inrush

current due to the dVOUT/dt of the output capaci-

tor COUT is:

VOUT

ICOUT = COUT*(0.4 V/ms) * 1.25

As Figure 1 shows, the SS voltage controls a

variety of signals. First, provided all the exter-

nal fault conditions are removed, an internal

5ÂµA pull-up at the COMP pin brings the SP6121

out of shutdown mode. The internal timing

circuit is then activated and controls the ramp-

up of the error amp reference voltage. The

COMP pin is pulled to 0.7V by the internal

Date: 11/29/04

SP6121 Low Voltage, Synchronous Step Down PWM Controller

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