SI5316 Datasheet, PDF (9/16 Pages) Silicon Laboratories – PRELIMINARY DATA SHEET PRECISION CLOCK JITTER ATTENUATOR

Si5316
Pin #
26
27
33
30
Table 3. Si5316 Pin Descriptions (Continued)
Pin Name I/O Signal Level
Description
CK1DIV I
3-Level
Input Clock 1 Pre-Divider Select.
Pre-divider on CKIN1. Used with CK2DIV to divide input clock
frequencies to a common value. When the frequencies applied to
CKIN1 and CKIN2 are equal, CK1DIV must be tied low.
L = CKIN1 input divider set to 1.
M = CKIN1 input divider set to 4.
H = CKIN1 input divider set to 32.
CK2DIV I
3-Level
Input Clock 2 Pre-Divider Select.
Pre-divider on CKIN2. Used with CK1DIV to divide input clock
frequencies to a common value. When the frequencies applied to
CKIN1 and CKIN2 are equal, CK2DIV must be tied low.
L = CKIN2 input divider set to 1.
M = CKIN2 input divider set to 4.
H = CKIN2 input divider set to 32.
SFOUT0 I
SFOUT1
3-Level
Signal Format Select.
Three level inputs that select the output signal format (common
mode voltage and differential swing) for CKOUT. Valid settings
include LVPECL, LVDS, and CML. Also includes selections for
CMOS mode, tristate mode, and tristate/sleep mode.
SFOUT[1:0]
HH
HM
HL
MH
MM
ML
LH
LM
LL
Signal Format
Reserved
Reserved
CML
LVPECL
Reserved
LVDS
CMOS
Tristate/Sleep
Reserved
34
CKOUT– O
35
CKOUT+
GND PAD GND GND
Multi
Supply
Clock Output.
Differential output clock with a frequency selected from a table of val-
ues. Output signal format is selected by SFOUT pins. Output is differ-
ential for LVPECL, LVDS, and CML compatible modes. For CMOS
format, both output pins drive identical single-ended clock outputs.
Ground Pad.
The ground pad must provide a low thermal and electrical impedance
to a ground plane.
Preliminary Rev. 0.24
9