SI5316 Datasheet, PDF (6/16 Pages) Silicon Laboratories – PRELIMINARY DATA SHEET PRECISION CLOCK JITTER ATTENUATOR

Si5316
1. Functional Description
The Si5316 is a precision jitter attenuator for high-speed
communication systems, including OC-48, OC-192,
10G Ethernet, and 10G Fibre Channel. The Si5316
accepts dual clock inputs in the 19, 38, 77, 155, 311, or
622 MHz frequency range and generates a jitter-
attenuated clock output at the same frequency. Within
each of these clock ranges, the device can be tuned
approximately 15% higher than nominal SONET/SDH
frequencies, up to a maximum of 710 MHz in the
622 MHz range. The Si5316 is based on Silicon
Laboratories' 3rd-generation DSPLL^® technology, which
provides any-rate frequency synthesis and jitter
attenuation in a highly integrated PLL solution that
eliminates the need for external VCXO and loop filter
components. For applications which require input clocks
at different frequencies, the frequency of CKIN1 can be
1x, 4x, or 32x the frequency of CKIN2 as specified by
the CK1DIV and CK2DIV inputs.
The Si5316 PLL loop bandwidth is selectable via the
BWSEL[1:0] pins and supports a range from 100 Hz to
7.9 kHz. To calculate potential loop bandwidth values
for a given input/output clock frequency, Silicon
Laboratories offers a PC-based software utility,
DSPLLsim, that calculates valid loop bandwidth settings
automatically. This utility can be downloaded from
www.silabs.com/timing.
The Si5316 supports manual active input clock
selection. The Si5316 monitors both input clocks for
loss-of-signal and provides a LOS alarm when it detects
missing pulses on either input clock. Hitless switching is
not supported by the Si5316. During a clock transition,
the phase of the output clock will slew at a rate defined
by the PLL loop bandwidth until the original input clock
phase to output clock phase is restored. The device
monitors the lock status of the PLL. The lock detect
algorithm works by continuously monitoring the phase
of the input clock in relation to the phase of the
feedback clock.
The Si5316 has one differential clock output. The
electrical format of the clock output is programmable to
support LVPECL, LVDS, CML, or CMOS loads. For
system-level debugging, a bypass mode is available
which drives the output clock directly from the input
clock, bypassing the internal DSPLL. The device is
powered by a single 1.8, 2.5, or 3.3 V supply.
1.1. External Reference
An external, 38.88 MHz clock or a low-cost
114.285 MHz 3rd overtone crystal is used as part of a
fixed-frequency oscillator within the DSPLL. This
external reference is required for the device to perform
jitter attenuation. Silicon Laboratories recommends
using a high-quality crystal from TXC (www.txc.com.tw),
part number 7MA1400014. An external 38.88 MHz
clock from a high quality OCXO or TCXO can also be
used as a reference for the device.
In digital hold, the DSPLL remains locked to this
external reference. Any changes in the frequency of this
reference when the DSPLL is in digital hold will be
tracked by the output of the device. Note that crystals
can have temperature sensitivities.
1.2. Further Documentation
Consult the Silicon Laboratories Any-Rate Precision
Clock Family Reference Manual (FRM) for more
detailed information about the Si5316. The FRM can be
downloaded from www.silabs.com/timing.
Silicon Laboratories has developed a PC-based
software utility called DSPLLsim to simplify device
configuration, including frequency planning and loop
bandwidth selection. This utility can be downloaded
from www.silabs.com/timing.
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Preliminary Rev. 0.24