SI5316 Datasheet, PDF (8/16 Pages) Silicon Laboratories – PRELIMINARY DATA SHEET PRECISION CLOCK JITTER ATTENUATOR

Si5316
Pin #
7
6
8, 31
15
12
13
14
16
17
18
21
23
22
25
24
Table 3. Si5316 Pin Descriptions (Continued)
Pin Name I/O Signal Level
Description
XB
I
Analog External Crystal or Reference Clock.
XA
External crystal should be connected to these pins to use internal
oscillator based reference. If external reference is used, apply refer-
ence clock to XA input and leave XB pin floating. External reference
must be from a high-quality clock source (TCXO, OCXO). Frequency
of crystal or external clock is set by the RATE pin.
GND GND
Supply
Ground.
Must be connected to system ground. Minimize the ground path
impedance for optimal performance of this device.
RATE
I
3-Level
External Crystal or Reference Clock Rate.
Three level input that selects the type and rate of external crystal or
reference clock to be applied to the XA/XB port.
L = 38.88 MHz external clock
M = 114.285 MHz 3rd OT crystal
H = Reserved
CKIN2+ I
CKIN2–
Multi
Clock Input 2.
Differential input clock. This input can also be driven with a single-
ended signal.
DBL_BY I
3-Level
Output Disable/Bypass Mode Control.
Controls enable of CKOUT divider/output buffer path and PLL
bypass mode.
L = CKOUT enabled
M = CKOUT disabled
H = Bypass mode with CKOUT enabled
CKIN1+ I
CKIN1–
Multi
Clock Input 1.
Differential input clock. This input can also be driven with a single-
ended signal.
LOL
O LVCMOS PLL Loss of Lock Indicator.
This pin functions as the active high PLL loss of lock indicator.
0 = PLL locked
1 = PLL unlocked
CS
I
LVCMOS Input Clock Select.
This pin functions as the input clock selector. This input is internally
deglitched to prevent inadvertent clock switching during changes in
the CKSEL input state.
0 = Select CKIN1
1 = Select CKIN2
BWSEL1 I
BWSEL0
3-Level
Bandwidth Select.
Three level inputs that select the DSPLL closed loop bandwidth.
Detailed operations and timing characteristics for these pins may be
found in the Any-Rate Precision Clock Family Reference Manual.
FRQSEL1 I
FRQSEL0
3-Level
Frequency Select.
Sets the output frequency of the device. When the frequency of
CKIN1 is not equal to CKIN2, the lower frequency input clock must
be equal to the output clock frequency.
8
Preliminary Rev. 0.24