SI5316 Datasheet, PDF (7/16 Pages) Silicon Laboratories – PRELIMINARY DATA SHEET PRECISION CLOCK JITTER ATTENUATOR

2. Pin Descriptions: Si5316
Si5316
36 35 34 33 32 31 30 29 28
RST 1
27 CK2DIV
NC 2
26 CK1DIV
C1B 3
25 FRQSEL1
C2B 4
VDD 5
XA 6
GND
Pad
24 FRQSEL0
23 BWSEL1
22 BWSEL0
XB 7
21 _CS
GND 8
20 NC
NC 9
19 NC
10 11 12 13 14 15 16 17 18
Pin assignments are preliminary and subject to change.
Table 3. Si5316 Pin Descriptions
Pin # Pin Name I/O Signal Level
Description
1
RST
I
LVCMOS External Reset.
Active low input that performs external hardware reset of device.
Resets all internal logic to a known state. Clock outputs are tristated
during reset. After rising edge of RST signal, the Si5316 will perform
an internal self-calibration.
This pin has a weak pull-up.
2, 9, 11,
NC
19, 20,
28, 29, 36
3
C1B
—
—
No Connect.
These pins must be left unconnected for normal operation.
O LVCMOS CKIN1 Loss of Signal.
Active high Loss-of-signal indicator for CKIN1. Once triggered, the
alarm will remain active until CKIN1 is validated.
0 = CKIN1 present
1 = LOS on CKIN1
4
C2B
O LVCMOS CKIN2 Loss of Signal.
Active high Loss-of-signal indicator for CKIN2. Once triggered, the
alarm will remain active until CKIN2 is validated.
0 = CKIN2 present
1 = LOS on CKIN2
5, 10, 32
V_DD
V_DD
Supply Supply.
The device operates from a 1.8, 2.5, or 3.3 V supply. Bypass capaci-
tors should be associated with the following V_DD pins:
5
0.1 µF
10
0.1 µF
32
0.1 µF
A 1.0 µF should be placed as close to device as is practical.
Preliminary Rev. 0.24
7