CP2102N Datasheet, PDF (9/44 Pages) Silicon Laboratories – USBXpress Family

3.1.3 Reset and Supply Monitor
CP2102N Data Sheet
Electrical Specifications
Table 3.3. Reset and Supply Monitor
Parameter
Symbol
VDD Supply Monitor Threshold
V_VDDM
Power-On Reset (POR) Threshold V_POR
VDD Ramp Time
t_RMP
Reset Delay from POR
t_POR
Reset Delay from non-POR source t_RST
RSTb Low Time to Generate Reset t_RSTL
Test Condition
Rising Voltage on VDD
Falling Voltage on VDD
Time to V_DD > 2.2 V
Relative to V_DD > V_POR
Time between release of reset
source and code execution
Min
Typ
Max
Unit
1.95
2.05
2.15
V
—
1.2
—
V
0.75
—
1.36
V
10
—
—
μs
3
10
31
ms
—
50
—
μs
15
—
—
μs
3.1.4 Configuration Memory
Table 3.4. Configuration Memory
Parameter
Symbol Test Condition
Min
Typ
V_DD Voltage During Programming ^{1 V}PROG
2.2
—
Endurance (Write/Erase Cycles)
N_WE
20k
100k
Note:
1. The device can be safely programmed at any voltage above the supply monitor threshold (V_VDDM).
2. Data Retention Information is published in the Quarterly Quality and Reliability Report.
Max
Units
3.6
V
—
Cycles
3.1.5 Internal Oscillator
Parameter
Internal Oscillator Frequency
Power Supply Sensitivity
Temperature Sensitivity
Table 3.5. Internal Oscillator
Symbol
f_OSC
PSS_OSC
TS_OSC
Test Condition
Full Temperature and Supply
Range
T_A = 25 °C
V_DD = 3.0 V
Min
47.3
—
—
Typ
48
0.02
45
Max
Unit
48.7
MHz
—
%/V
—
ppm/°C
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