SI514 Datasheet, PDF (8/36 Pages) Silicon Laboratories – ANY-FREQUENCY IC PROGRAMMABLE XO

Si514
Table 6. Output Clock Jitter and Phase Noise (LVDS)
V_DD = 1.8 V ±5%, 2.5 or 3.3 V ±10%, T_A = –40 to +85 ^oC; Output Format = LVDS
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
Period Jitter
(RMS)
JPRMS
10k samples¹
—
—
2.1
ps
Period Jitter
(Pk-Pk)
JPPKPK
10k samples¹
—
—
18
ps
Phase Jitter
(RMS)
φJ
1.875 MHz to 20 MHz integration
—
0.25
0.55
ps
bandwidth² (brickwall)
Phase Noise,
156.25 MHz
12 kHz to 20 MHz integration
bandwidth² (brickwall)
—
0.8
1.0
ps
φN
100 Hz
—
–86
—
dBc/Hz
1 kHz
—
–109
—
dBc/Hz
10 kHz
—
–116
—
dBc/Hz
100 kHz
—
–123
—
dBc/Hz
Spurious
SPR
1 MHz
LVPECL output, 156.25 MHz,
offset>10 kHz
—
–136
—
dBc/Hz
—
–75
—
dBc
Notes:
1. Applies to output frequencies: 74.17582, 74.25, 75, 77.76, 100, 106.25, 125, 148.35165, 148.5, 150, 155.52, 156.25,
212.5, 250 MHz.
2. Applies to output frequencies: 100, 106.25, 125, 148.35165, 148.5, 150, 155.52, 156.25, 212.5 and 250 MHz.
8
Rev. 1.0