SI514 Datasheet, PDF (7/36 Pages) Silicon Laboratories – ANY-FREQUENCY IC PROGRAMMABLE XO

Si514
Table 5. Output Clock Jitter and Phase Noise (LVPECL)
V_DD = 2.5 or 3.3 V ±10%, T_A = –40 to +85 ^oC; Output Format = LVPECL
Parameter
Symbol
Period Jitter (RMS) JPRMS
Period Jitter (Pk-Pk) JPPKPK
Test Condition
10 k samples¹
10 k samples¹
Min
Typ
Max
Units
—
—
1.3
ps
—
—
11
ps
Phase Jitter (RMS)
φJ
1.875 MHz to 20 MHz integration
—
0.31
0.5
ps
bandwidth² (brickwall)
12 kHz to 20 MHz integration
—
0.8
1.0
ps
bandwidth²
Phase Noise,
φN
156.25 MHz
100 Hz
1 kHz
—
–86
—
dBc/Hz
—
–109
—
dBc/Hz
10 kHz
—
–116
—
dBc/Hz
100 kHz
—
–123
—
dBc/Hz
1 MHz
—
–136
—
dBc/Hz
Additive RMS
Jitter Due to Power
Supply Noise³
JPSR
10 kHz sinusoidal noise
100 kHz sinusoidal noise
500 kHz sinusoidal noise
—
3.0
—
ps
—
3.5
—
ps
—
3.5
—
ps
1 MHz sinusoidal noise
—
3.5
—
ps
Spurious
SPR
LVPECL output, 156.25 MHz,
—
–75
—
dBc
offset > 10 kHz
Notes:
1. Applies to output frequencies: 74.17582, 74.25, 75, 77.76, 100, 106.25, 125, 148.35165, 148.5, 150, 155.52, 156.25,
212.5, 250 MHz.
2. Applies to output frequencies: 100, 106.25, 125, 148.35165, 148.5, 150, 155.52, 156.25, 212.5 and 250 MHz.
3. 156.25 MHz. Increase in jitter on output clock due to sinewave noise added to VDD (2.5/3.3 V = 100 mVPP).
Rev. 1.0
7