SI8660BA-B-IS1 Datasheet, PDF (7/40 Pages) Silicon Laboratories – LOW POWER SIX-CHANNEL DIGITAL ISOLATOR

Si8660/61/62/63
Table 2. Electrical Characteristics (Continued)
(V_DD1 = 5 V ±10%, V_DD2 = 5 V ±10%, T_A = –40 to 125 °C)
Parameter
Symbol
Test Condition
Min
Typ
Max Unit
Timing Characteristics
Si866xBx, Ex
Maximum Data Rate
0
—
150 Mbps
Minimum Pulse Width
—
—
5.0
ns
Propagation Delay
Pulse Width Distortion
|t_PLH - t_PHL|
Propagation Delay
Skew²
Channel-Channel Skew
All Models
Output Rise Time
t_PHL, t_PLH
PWD
t_PSK(P-P)
t_PSK
t_r
See Figure 1
See Figure 1
C_L = 15 pF
(See Figure 1)
5.0
8.0
13
ns
—
0.2
4.5
ns
—
2.0
4.5
ns
—
0.4
2.5
ns
—
2.5
4.0
ns
Output Fall Time
t_f
C_L = 15 pF
(See Figure 1)
—
2.5
4.0
ns
Peak Eye Diagram Jitter t_JIT(PK)
See Figure 7
—
350
—
ps
Common Mode
Transient Immunity
CMTI
V_I = V_DD or 0 V
V_CM = 1500 V
(See Figure 2)
35
50
— kV/µs
Startup Time³
t_SU
—
15
40
µs
Notes:
1. The nominal output impedance of an isolator driver channel is approximately 50 , ±40%, which is a combination of
the value of the on-chip series termination resistor and channel resistance of the output driver FET. When driving loads
where transmission line effects will be a factor, output pins should be appropriately terminated with controlled
impedance PCB traces.
2. t_PSK(P-P) is the magnitude of the difference in propagation delay times measured between different units operating at
the same supply voltages, load, and ambient temperature.
3. Start-up time is the time period from the application of power to valid data at the output.
1.4 V
Typical
Input
1.4 V
Typical
Output
t_PLH
t_PHL
90%
10%
90%
10%
t_r
t_f
Figure 1. Propagation Delay Timing
Rev. 1.5
7