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SI5540 Datasheet, PDF (7/20 Pages) Silicon Laboratories – SiPHY OC-192/STM-64 TRANSMITTER
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Si5540
Table 3. AC Characteristics (TXCLK16OUT, TXCLK16IN, TXCLKOUT, TXDIN, TXDOUT)
(VDD = 1.8 V ±5%, TA = –40°C to 85°C)
Parameter
Symbol
Test Condition
Min
Typ
Max
TXCLKOUT Frequency
TXCLKOUT Duty Cycle
fclkout
tch/tcp, Figure 2
—
9.95 10.7
45
—
55
Output Rise Time
tR
(TXCLKOUT, TXDOUT)
Output Fall Time
tF
(TXCLKOUT, TXDOUT)
TXCLKOUT Setup to TXDOUT
tsu
TXCLKOUT Hold From TXDOUT thd
Output Return Loss
Figure 3
Figure 3
Figure 2
Figure 2
400 kHz–10 GHz
10 GHz–16 GHz
—
25
—
—
25
—
25
—
—
25
—
—
TBD
—
—
TBD
—
—
TXCLK16OUT Frequency
TXCLK16OUT Duty Cycle
fCLKIN
Figure 2
tch/tcp, Figure 2
—
622
667
40
—
60
TXCLK16OUT Rise & Fall Times
TXDIN Setup to TXCLK16IN
TXDIN Hold from TXCLK16IN
TXCLK16IN Frequency
TXCLK16IN Duty Cycle
tR, tF
tDSIN
tDHIN
fCLKIN
tch/tcp, Figure 2
100
—
300
—
—
300
—
—
300
—
622
667
40
—
60
TXCLK16IN Rise & Fall Times
tR, tF
100
—
300
Unit
GHz
%
ps
ps
ps
ps
dB
dB
MHz
%
ps
ps
ps
MHz
%
ps
Table 4. AC Characteristics (Clock Multiplier Characteristics)
(VDD = 1.8 V ±5%, TA = –40°C to 85°C)
Parameter
Jitter Generation—Deterministic
Jitter Generation—Random
Jitter Transfer Bandwidth
Symbol
JDET(PP)
JGEN(RMS)
JBW
Jitter Transfer Peaking
Acquisition Time
TAQ
Input Reference Clock Frequency RCFREQ
Test Condition
PRBS-23
BWSEL = 0
BWSEL = 1
Valid REFCLK
REFRATE = 1
REFRATE = 0
Input Reference Clock Duty
Cycle
RCDUTY
Input Reference Clock Frequency RCTOL
Tolerance
Note: Bellcore specifications: GR-1377-CORE, Issue 5, December 1998.
Min
Typ
Max Unit
—
0.020 TBD UIPP
—
0.005 TBD UIRMS
—
—
12
kHz
—
—
50
kHz
—
0.05
0.1
dB
—
15
20
ms
—
622
667 MHz
—
155
167 MHz
40
—
60
%
–100
—
100 ppm
Preliminary Rev. 0.31
7
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