SI5540 Datasheet, PDF (15/20 Pages) Silicon Laboratories – SiPHY OC-192/STM-64 TRANSMITTER

Si5540
Pin Number(s)
Pin Name
I/O
J1
REXT
D3, E3, F3, G3, RSVD_GND
—
J3
A3, B2
RSVD_VDD33 —
K5–6
TXCLK16IN–,
I
TXCLK16IN+
K3–4
TXCLK16OUT+, O
TXCLK16OUT–
B4
TXCLKDSBL
I
C1, D1
TXCLKOUT+,
O
TXCLKOUT–
A7–10, B5–10, TXDIN[15:0]–,
I
C9–10, D9–10, TXDIN[15:0]+
E9–10, F9–10,
G9–10, H9–10,
J5–10, K7–10
F1, G1
TXDOUT+,
O
TXDOUT–
J2
TXLOL
O
Signal Level
Description
External Bias Resistor.
This resistor is used by onboard circuitry to
establish bias currents within the device. This
pin must be connected to GND through a
3.09 kΩ (1%) resistor.
Reserved Tie to Ground.
Must tie directly to GND for proper operation.
Reserved Tie to VDD33.
Must tie directly to VDD33 for proper operation.
LVDS
LVDS
Differential Data Clock Input.
The rising edge of this input clocks data present
on TXDIN into the device.
Divided Down Output Clock.
This clock output is generated by dividing down
the high speed output clock, TXCLKOUT, by a
factor of 16. It is intended for use in counter
clocking schemes that transfer data between
the system ASIC and the Si5540.
LVTTL
High Speed Clock Disable.
When this input is high, the output driver for
TXCLKOUT is disabled. In applications that do
not require the output data clock, the output
clock driver should be disabled to save power.
CML
High Speed Clock Output.
The high speed output clock, TXCLKOUT, is
generated by the PLL in the clock multiplier
unit. It’s frequency is nominally 16 or 64 times
the selected reference source.
LVDS
CML
Differential Parallel Data Input.
The 16-bit data word present on these pins is
multiplexed into a high speed serial stream and
output on TXDOUT. The data on these inputs is
clocked into the device by the rising edge of
TXCLKIN.
Differential High Speed Data Output.
The 16-bit word input on TXDIN[15:0] is multi-
plexed into a high speed serial stream that is
output on these pins. This output is updated by
the rising edge of TXCLKOUT.
LVTTL
CMU Loss-of-Lock.
The output is asserted low when the CMU is not
phase locked to the selected reference source.
Preliminary Rev. 0.31
15