SI5366 Datasheet, PDF (7/20 Pages) Silicon Laboratories – PRECISION CLOCK MULTIPLIER/JITTER ATTENUATOR

2. Pin Descriptions: Si5366
Si5366
NC
NC
RST
FRQTBL
VDD
VDD
GND
GND
C1B
C2B
C3B
ALRMOUT
CS0_C3A
GND
VDD
XA
XB
GND
GND
FS_SW
FS_ALIGN
AUTOSEL
NC
NC
NC
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76
1
75
2
74
3
73
4
72
5
71
6
70
7
69
8
68
9
67
10
66
11
65
12
64
13
Si5366
63
14
62
15
61
16
60
17
59
18
58
19
GND PAD
57
20
56
21
55
22
54
23
53
24
52
25
51
26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 ^{41 42 43 44 45 46 47 48 49 50}
NC
NC
NC
NC
FRQSEL3
FRQSEL2
FRQSEL1
FRQSEL0
DIV34_1
DIV34_0
GND
GND
VDD
VDD
BWSEL1
BWSEL0
C2A
C1A
CS1_C4A
FOS_CTL
INC
DEC
NC
NC
CK_CONF
Pin #
1, 2, 23, 24,
25, 32, 47,
48, 52, 53,
72, 73, 74,
75, 90
3
Pin Name
NC
RST
Table 3. Si5366 Pin Descriptions
I/O Signal Level
Description
No Connect.
These pins must be left unconnected for normal operation.
I
LVCMOS External Reset.
Active low input that performs external hardware reset of
device. Resets all internal logic to a known state and forces the
device registers to their default value. Clock outputs are
tristated during reset. After rising edge of RST signal, the
device will perform an internal self-calibration.
This pin has a weak pull-up.
Preliminary Rev. 0.2
7