SI5366 Datasheet, PDF (10/20 Pages) Silicon Laboratories – PRECISION CLOCK MULTIPLIER/JITTER ATTENUATOR

Si5366
Pin #
29
30
42
34
35
37
39
40
44
45
49
50
51
Pin Name
CKIN4+
CKIN4–
RATE
CKIN2+
CKIN2–
DBL2_BY
CKIN3+
CKIN3–
CKIN1+
CKIN1–
LOL
DBL_FS
CK_CONF
Table 3. Si5366 Pin Descriptions (Continued)
I/O Signal Level
Description
I
MULTI Clock Input 4.
Differential clock input. This input can also be driven with a sin-
gle-ended signal. CKIN4 serves as the frame sync input asso-
ciated with the CKIN2 clock when CK_CONF = 1.
I
3-Level External Crystal or Reference Clock Rate.
Three level input that selects the type and rate of external crys-
tal or reference clock to be applied to the XA/XB port.
L = 38.88 MHz external clock.
M = 114.285 MHz 3rd OT crystal.
H = Reserved.
I
MULTI Clock Input 2.
Differential input clock. This input can also be driven with a sin-
gle-ended signal.
I
3-Level CKOUT2 Disable/PLL Bypass Mode Control.
Controls enable of CKOUT2 divider/output buffer path and PLL
bypass mode.
L = CKOUT2 Enabled.
M = CKOUT2 Disabled.
H = BYPASS Mode with CKOUT2 enabled.
I
MULTI Clock Input 3.
Differential clock input. This input can also be driven with a sin-
gle-ended signal. CKIN3 serves as the frame sync input asso-
ciated with the CKIN1 clock when CK_CONF = 1.
I
MULTI Clock Input 1.
Differential clock input. This input can also be driven with a sin-
gle-ended signal.
O LVCMOS PLL Loss of Lock Indicator.
This pin functions as the active high PLL loss of lock indicator.
0 = PLL locked.
1 = PLL unlocked.
I
3-Level FS_OUT Disable.
This pin performs the following functions:
L = Normal operation. Output path is active and signal format is
determined by SFOUT inputs.
M = CMOS signal format. Overrides SFOUT signal format to
allow FS_OUT to operate in CMOS format while the clock out-
puts operate in a differential output format.
H = Powerdown. Entire FS_OUT divider and output buffer path
is powered down. FS_OUT output will be in tristate mode dur-
ing powerdown.
I
LVCMOS Input Clock Configuration Control.
This pin controls the input clock configuration.
0 = CKIN1, 2, 3, 4 inputs, no FS_OUT alignment.
1 = CKIN1, 3 and CKIN2, 4 clock/FSYNC pairs.
This pin has a weak pull-down.
10
Preliminary Rev. 0.2