SI5366 Datasheet, PDF (12/20 Pages) Silicon Laboratories – PRECISION CLOCK MULTIPLIER/JITTER ATTENUATOR

Si5366
Pin #
66
67
68
69
70
71
77
78
80
95
82
83
85
Pin Name
DIV34_0
DIV34_1
FRQSEL0
FRQSEL1
FRQSEL2
FRQSEL3
CKOUT3+
CKOUT3–
SFOUT1
SFOUT0
CKOUT1–
CKOUT1+
DBL34
Table 3. Si5366 Pin Descriptions (Continued)
I/O Signal Level
Description
I
3-Level CKOUT3 and CKOUT4 Divider Control.
These pins control the division of CKOUT3 and CKOUT4 rela-
tive to the CKOUT2 output frequency. Detailed operations and
timing characteristics for these pins may be found in the Any-
Rate Precision Clock Family Reference Manual.
I
3-Level Multiplier Select.
These pins are three level inputs that select the input clock and
clock multiplication setting according to the Any-Rate Precision
Clock Family Reference Manual, depending on the FRQTBL
setting.
O
MULTI Clock Output 3.
Differential output clock with a frequency specified by FRQSEL
and FRQTBL settings. Output is differential for LVPECL, LVDS,
and CML compatible modes. For CMOS format, both output
pins drive identical single-ended clock outputs.
I
3-Level Signal Format Select.
Three level inputs that select the output signal format (common
mode voltage and differential swing) for all of the clock outputs
and FS_OUT.
SFOUT[1:0]
Signal Format
HH
Reserved
HM
Reserved
HL
CML
MH
LVPECL
MM
Reserved
ML
LVDS
LH
CMOS
LM
Tristate/Sleep
LL
Reserved
O
MULTI Clock Output 1.
Differential output clock with a frequency specified by FRQSEL
and FRQTBL. Output signal format is selected by SFOUT pins.
Output is differential for LVPECL, LVDS, and CML compatible
modes. For CMOS format, both output pins drive identical sin-
gle-ended clock outputs.
I
LVCMOS Output 3 and 4 Disable.
Active high input. When active, entire CKOUT3 and CKOUT4
divider and output buffer path is powered down. CKOUT3 and
CKOUT4 outputs will be in tristate mode during powerdown.
This pin has a weak pull-down.
12
Preliminary Rev. 0.2