SI5366 Datasheet, PDF (13/20 Pages) Silicon Laboratories – PRECISION CLOCK MULTIPLIER/JITTER ATTENUATOR

Si5366
Pin #
87
88
92
93
97
98
GND PAD
Pin Name
FS_OUT–
FS_OUT+
CKOUT2+
CKOUT2–
CKOUT4–
CKOUT4+
GND PAD
Table 3. Si5366 Pin Descriptions (Continued)
I/O Signal Level
Description
O
MULTI Frame Sync Output.
Differential 8 kHz frame sync output or fifth high-speed clock
output with a frequency specified by FRQSEL and FRQTBL.
Output signal format is selected by SFOUT pins. Detailed oper-
ations and timing characteristics for this pin may be found in
the Any-Rate Precision Clock Family Reference Manual. Out-
put is differential for LVPECL, LVDS, and CML compatible
modes. For CMOS format, both output pins drive identical sin-
gle-ended clock outputs.
O
MULTI Clock Output 2.
Differential output clock with a frequency specified by FRQSEL
and FRQTBL. Output signal format is selected by SFOUT pins.
Output is differential for LVPECL, LVDS, and CML compatible
modes. For CMOS format, both output pins drive identical sin-
gle-ended clock outputs.
O
MULTI Clock Output 4.
Differential output clock with a frequency specified by FRQSEL
and FRQTBL settings. Output signal format is selected by
SFOUT pins. Output is differential for LVPECL, LVDS, and
CML compatible modes. For CMOS format, both output pins
drive identical single-ended clock outputs.
GND
Supply
Ground Pad.
The ground pad must provide a low thermal and electrical
impedance to a ground plane.
Preliminary Rev. 0.2
13