SI5366 Datasheet, PDF (1/20 Pages) Silicon Laboratories – PRECISION CLOCK MULTIPLIER/JITTER ATTENUATOR

Si5366
PRELIMINARY DATA SHEET
PRECISION CLOCK MULTIPLIER/JITTER ATTENUATOR
Description
The Si5366 is a jitter-attenuating precision clock
multiplier for high-speed communication systems,
including SONET OC-48/OC-192, Ethernet, and Fibre
Channel. The Si5366 accepts four clock inputs ranging
from 8 kHz to 707 MHz and generates five frequency-
multiplied clock outputs ranging from 8 kHz to
1050 MHz. The input clock frequency and clock
multiplication ratio are selectable from a table of
popular SONET, Ethernet, and Fibre Channel rates.
The Si5366 is based on Silicon Laboratories' 3rd-
generation DSPLL^® technology, which provides any-
rate frequency synthesis and jitter attenuation in a
highly integrated PLL solution that eliminates the need
for external VCXO and loop filter components. The
DSPLL loop bandwidth is digitally programmable,
providing jitter performance optimization at the
application level. Operating from a single 1.8 or 2.5 V
supply, the Si5366 is ideal for providing clock
multiplication and jitter attenuation in high performance
timing applications.
Applications
„ SONET/SDH OC-48/OC-192 line cards
„ GbE/10GbE, 1/2/4/8/10GFC line cards
„ ITU G.709 line cards
„ Optical modules
„ Test and measurement
Features
„ Selectable output frequencies ranging from 8 kHz to
1050 MHz
„ Ultra-low jitter clock outputs w/jitter generation as
low as 0.3 ps rms (50 kHz–80 MHz)
„ Integrated loop filter with selectable loop bandwidth
(60 Hz to 8.4 kHz)
„ Meets OC-192 GR-253-CORE jitter specifications
„ Four clock inputs w/manual or automatically
controlled hitless switching
„ Five clock outputs with selectable signal format
(LVPECL, LVDS, CML, CMOS)
„ SONET frame sync switching and regeneration
„ Support for ITU G.709 FEC ratios (255/238,
255/237, 255/236)
„ LOL, LOS, FOS alarm outputs
„ Pin-controlled output phase adjust
„ Pin-programmable settings
„ On-chip voltage regulator for 1.8 or 2.5 V ±10%
operation
„ Small size: 14 x 14 mm 100-pin TQFP
„ Pb-free, RoHS compliant
Xtal or Refclock
CKIN1
CKIN2
CKIN3
CKIN4
Input Clock Configuration
Manual/Auto Switch
Clock Select
Resonator/Rate Select
LOL/LOS/FOS Alarms
Frequency Select
Bandwidth Select
Latency Control
FSYNC Align
Control
DSPLL^®
÷
÷
Output Clock2
Input Clock3
Input Clock4
÷ NFS
CKOUT1
CKOUT2
CKOUT3
Divider Select
CKOUT4
CKOUT5 (FS_OUT)
VDD (1.8 or 2.5 V)
GND
Preliminary Rev. 0.2 3/07
Copyright © 2007 by Silicon Laboratories
Si5366
This information applies to a product under development. Its characteristics and specifications are subject to change without notice.