SI5319 Datasheet, PDF (7/16 Pages) Silicon Laboratories – ANY-RATE PRECISION CLOCK MULTIPLIER/JITTER ATTENUATOR

2. Pin Descriptions: Si5319
Si5319
36 35 34 33 32 31 30 29 28
RST 1
27 SDI
NC 2
26 A2_SS
INT_CB 3
25 A1
NC 4
VDD 5
XA 6
GND
Pad
24 A0
23 SDA_SDO
22 SCL
XB 7
21 _CS
GND 8
20 GND
NC 9
19 GND
10 11 12 13 14 15 16 17 18
Pin numbers are preliminary and subject to change.
Pin # Pin Name I/O Signal Level
Description
1
RST
2, 4, 9,
NC
12–14,
30,
33–35
I
LVCMOS ^{External Reset.}
Active low input that performs external hardware reset of device.
Resets all internal logic to a known state and forces the device regis-
ters to their default value. Clock outputs are disabled during reset. The
part must be programmed after a reset or power-on to get a clock out-
put. See Family Reference Manual for details.
This pin has a weak pull-up.
—
—
No Connect.
This pin must be left unconnected for normal operation.
3
INT_CB O LVCMOS ^{Interrupt/CKIN Invalid Indicator.}
This pin functions as a device interrupt output or an alarm output for
CKIN. If used as an interrupt output, INT_PIN must be set to 1. The pin
functions as a maskable interrupt output with active polarity controlled
by the INT_POL register bit.
If used as an alarm output, the pin functions as a LOS alarm indicator
for CKIN. Set CK_BAD_PIN = 1 and INT_PIN = 0.
0 = CKIN present.
1 = LOS on CKIN.
The active polarity is controlled by CK_BAD_POL. If no function is
selected, the pin tristates.
Note: Internal register names are indicated by underlined italics (e.g., INT_PIN. See Si5319 Register Map).
Preliminary Rev. 0.3
7