SI5319 Datasheet, PDF (6/16 Pages) Silicon Laboratories – ANY-RATE PRECISION CLOCK MULTIPLIER/JITTER ATTENUATOR

Si5319
1. Functional Description
The Si5319 is a jitter-attenuating precision clock
multiplier for applications requiring sub 1 ps jitter
performance. The Si5319 accepts one clock input
ranging from 2 kHz to 710 MHz and generates one
clock output ranging from 2 kHz to 945 MHz and select
frequencies to 1.4 GHz. The Si5319 can also use its
crystal oscillator as a clock source for frequency
synthesis. The device provides virtually any frequency
translation combination across this operating range.
The Si5319 input clock frequency and clock
multiplication ratio are programmable through an I²C or
SPI interface. Silicon Laboratories offers a PC-based
software utility, DSPLLsim, that can be used to
determine the optimum PLL divider settings for a given
input frequency/clock multiplication ratio combination
that minimizes phase noise and power consumption.
This utility can be downloaded from
http://www.silabs.com/timing.
The Si5319 is based on Silicon Laboratories' 3rd-
generation DSPLL^® technology, which provides any-
rate frequency synthesis and jitter attenuation in a
highly integrated PLL solution that eliminates the need
for external VCXO and loop filter components. The
Si5319 PLL loop bandwidth is digitally programmable
and supports a range from 60 Hz to 8.4 kHz. The
DSPLLsim software utility can be used to calculate valid
loop bandwidth settings for a given input clock
frequency/clock multiplication ratio.
The Si5319 monitors the input clock for loss-of-signal
and provides a LOS alarm when it detects missing
pulses on the input clock. The device monitors the lock
status of the PLL. The lock detect algorithm works by
continuously monitoring the phase of the input clock in
relation to the phase of the feedback clock.
The Si5319 provides a digital hold capability that allows
the device to continue generation of a stable output
clock when the selected input reference is lost. During
digital hold, the DSPLL freezes its VCO settings and
uses its XO as its frequency reference.
The Si5319 has one differential clock output. The
electrical format of the clock output is programmable to
support LVPECL, LVDS, CML, or CMOS loads. For
system-level debugging, a bypass mode is available
which drives the output clock directly from the input
clock, bypassing the internal DSPLL. The device is
powered by a single 1.8, 2.5, or 3.3 V supply.
1.1. External Reference
A low-cost 114.285 MHz 3rd overtone crystal or an
external reference oscillator is used as part of a fixed-
frequency oscillator within the DSPLL. This external
reference is required for the device to perform jitter
attenuation. Silicon Laboratories recommends using a
high quality crystal. Specific recommendations may be
found in the Family Reference Manual. An external
oscillator as well as other crystal frequencies can also
be used as a reference for the device.
In digital hold, the DSPLL remains locked to this
external reference. Any changes in the frequency of this
reference when the DSPLL is in digital hold will be
tracked by the output of the device. Note that crystals
can have temperature sensitivities.
1.2. Further Documentation
Consult the Silicon Laboratories Any-Rate Precision
Clock Family Reference Manual (FRM) for detailed
information about the Si5319. Additional design support
is available from Silicon Laboratories through your
distributor.
Silicon Laboratories has developed a PC-based
software utility called DSPLLsim to simplify device
configuration, including frequency planning and loop
bandwidth selection. The FRM and this utility can be
downloaded from http://www.silabs.com/timing; click on
Documentation.
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