SI5319 Datasheet, PDF (1/16 Pages) Silicon Laboratories – ANY-RATE PRECISION CLOCK MULTIPLIER/JITTER ATTENUATOR

Si5319
PRELIMINARY DATA SHEET
ANY-RATE PRECISION CLOCK MULTIPLIER/JITTER ATTENUATOR
Description
The Si5319 is a jitter-attenuating precision M/N clock
multiplier for applications requiring sub 1 ps jitter
performance. The Si5319 accepts one clock input ranging
from 2 kHz to 710 MHz and generates one clock output
ranging from 2 kHz to 945 MHz and select frequencies to
1.4 GHz. The Si5319 can also use its crystal oscillator as a
clock source for frequency synthesis. The device provides
virtually any frequency translation combination across this
operating range. The Si5319 input clock frequency and clock
multiplication ratio are programmable through an I²C or SPI
interface. The Si5319 is based on Silicon Laboratories' 3rd-
generation DSPLL^® technology, which provides any-rate
frequency synthesis and jitter attenuation in a highly
integrated PLL solution that eliminates the need for external
VCXO and loop filter components. The DSPLL loop
bandwidth is digitally programmable, providing jitter
performance optimization at the application level. Operating
from a single 1.8, 2.5, or 3.3 V supply, the Si5319 is ideal for
providing clock multiplication and jitter attenuation in high
performance timing applications.
Applications
SONET/SDH OC-48/STM-16 and OC-192/STM-64
line cards
GbE/10GbE, 1/2/4/8/10GFC line cards
ITU G.709 and custom FEC line cards
Optical modules
Wireless basestations
Data converter clocking
xDSL
Synchronous Ethernet
Test and measurement
Discrete PLL replacement
Broadcast video
Xtal or Refclock
Features
Generates any frequency from 2 kHz to 945 MHz
and select frequencies to 1.4 GHz from an input
frequency of 2 kHz to 710 MHz
Ultra-low jitter clock outputs with jitter generation as
low as 0.3 ps rms (50 kHz–80 MHz)
Integrated loop filter with selectable loop bandwidth
(60 Hz to 8.4 kHz)
Meets OC-192 GR-253-CORE jitter specifications
Clock or crystal input with manual clock selection
Clock output selectable signal format
(LVPECL, LVDS, CML, CMOS)
Support for ITU G.709 and custom FEC ratios
(255/238, 255/237, 255/236)
Supports various frequency translations for
Synchronous Ethernet
LOL, LOS alarm outputs
I²C or SPI programmable
On-chip voltage regulator for 1.8 V ±5%, 2.5 or
3.3 V ±10% operation
Small size: 6 x 6 mm 36-lead QFN
Pb-free, ROHS compliant
CKIN
XO
÷ N32
÷ N31
DSPLL^®
N1_HS
÷ NC1_LS
÷ N2
CKOUT
Loss of Signal
Loss of Lock
Signal Detect
Control
VDD (1.8, 2.5, or 3.3 V)
GND
I²C/SPI Port
Device Interrupt
Rate Select
Xtal/Clock Select
Preliminary Rev. 0.3 1/08
Copyright © 2008 by Silicon Laboratories
Si5319
This information applies to a product under development. Its characteristics and specifications are subject to change without notice.