SI5319 Datasheet, PDF (3/16 Pages) Silicon Laboratories – ANY-RATE PRECISION CLOCK MULTIPLIER/JITTER ATTENUATOR

Si5319
Table 1. Performance Specifications¹ (Continued)
(V_DD = 1.8 ±5%, 2.5 ±10%, or 3.3 V ±10%, T_A = –40 to 85 ºC)
Parameter
Symbol
Test Condition
Min
Typ
Max Unit
PLL Performance
Jitter Generation
J_GEN
f_IN = f_OUT = 622.08 MHz,
—
LVPECL output format
0.3
TBD ps rms
50 kHz–80 MHz
12 kHz–20 MHz
—
0.3
TBD ps rms
800 Hz–80 MHz
—
0.4
TBD ps rms
Jitter Transfer
J_PK
External Reference Jitter J_PKEXTN
Transfer
—
0.05
0.1
dB
—
TBD
TBD
dB
Phase Noise
CKO_PN
f_IN = f_OUT = 622.08 MHz
—
TBD
TBD dBc/Hz
100 Hz offset
1 kHz offset
—
TBD
TBD dBc/Hz
10 kHz offset
—
TBD
TBD dBc/Hz
100 kHz offset
—
TBD
TBD dBc/Hz
1 MHz offset
—
TBD
TBD dBc/Hz
Subharmonic Noise
Spurious Noise
SP_SUBH Phase Noise @ 100 kHz Offset
—
SP_SPUR
Max spur @ n x F3
—
(n > 1, n x F3 < 100 MHz)
TBD
TBD
TBD
dBc
TBD
dBc
Package
Thermal Resistance
Theta JA
Still Air
—
38
—
ºC/W
Junction to Ambient
Notes:
1. For a more comprehensive listing of device specifications, consult the Silicon Laboratories Any-Rate Precision Clock
Family Reference Manual.
2. This is the amount of leakage that the 3-level input can tolerate from an external driver. See the Family Reference
Manual. In most designs an external resistor voltage divider is recommended.
Table 2. Absolute Maximum Ratings
Parameter
Symbol
Value
Unit
DC Supply Voltage
V_DD
–0.5 to 3.6
V
LVCMOS Input Voltage
V_DIG
–0.3 to (V_DD + 0.3)
V
Operating Junction Temperature
T_JCT
–55 to 150
ºC
Storage Temperature Range
T_STG
–55 to 150
ºC
ESD HBM Tolerance (100 pF, 1.5 kΩ), Except CKIN Pins
2
kV
ESD HBM Tolerance (100 pF, 1.5 kΩ), CKIN Pins
700
V
ESD MM Tolerance, Except CKIN Pins
200
V
ESD MM Tolernace, CKIN Pins
150
V
Latch-Up Tolerance
JESD78 Compliant
Note: Permanent device damage may occur if the Absolute Maximum Ratings are exceeded. Functional operation should be
restricted to the conditions as specified in the operation sections of this data sheet. Exposure to absolute maximum
rating conditions for extended periods of time may affect device reliability.
Preliminary Rev. 0.3
3