SI5319 Datasheet, PDF (2/16 Pages) Silicon Laboratories – ANY-RATE PRECISION CLOCK MULTIPLIER/JITTER ATTENUATOR

Si5319
Table 1. Performance Specifications¹
(V_DD = 1.8 ±5%, 2.5 ±10%, or 3.3 V ±10%, T_A = –40 to 85 ºC)
Parameter
Symbol
Test Condition
Min
Typ
Max Unit
Temperature Range
T_A
Supply Voltage
V_DD
–40
25
85
ºC
2.97
3.3
3.63
V
2.25
2.5
2.75
V
1.71
1.8
1.89
V
Supply Current
I_DD
f_OUT = 622.08 MHz
CKOUT enabled
—
217
243
mA
LVPECL format output
f_OUT = 19.44 MHz
CKOUT enabled
—
194
220
mA
CMOS format output
Tristate/Sleep Mode
—
165
TBD
mA
Input Clock Frequency
CK_F Input frequency and clock multi- 0.002
—
(CKIN)
plication ratio determined by
710
MHz
Output Clock Frequency CK_OF ^{programming device PLL divid-} 0.002
—
(CKOUT)
ers. Consult Silicon Laboratories ₉₇₀
configuration software DSPLL- ₁₂₁₃
sim to determine PLL divider
945
1134
1400
MHz
settings for a given input fre-
quency/clock multiplication ratio
combination.
3-Level Input Pins
Input Mid Current
I_IMM
Input Clock (CKIN)
See Note 2.
–2
—
2
µA
Differential Voltage
Swing
CKN_DPP
0.25
—
1.9
VPP
Common Mode Voltage CKN_VCM
1.8 V ±5%
2.5 V ±10%
0.9
—
1.4
V
1.0
—
1.7
V
3.3 V ±10%
1.1
—
1.95
V
Rise/Fall Time
Duty Cycle
(Minimum Pulse Width)
CKN_TRF
CKN_DC
20–80%
Whichever is smaller
—
—
11
ns
40
—
60
%
2
—
—
ns
Output Clock (CKOUT)
Common Mode
Differential Output Swing
Single Ended Output
Swing
V_OCM
V_OD
V_SE
LVPECL
100 Ω load
line-to-line
V_DD – 1.42
—
V_DD – 1.25 V
1.1
—
1.9
0.5
—
0.93
V
Rise/Fall Time
Output Duty Cycle
Differential Uncertainty
CKO_TRF
CKO_DC
20–80%
100 Ω load
line-to-line
—
230
350
ps
—
—
±40
ps
measured at 50% point
Notes:
1. For a more comprehensive listing of device specifications, consult the Silicon Laboratories Any-Rate Precision Clock
Family Reference Manual.
2. This is the amount of leakage that the 3-level input can tolerate from an external driver. See the Family Reference
Manual. In most designs an external resistor voltage divider is recommended.
2
Preliminary Rev. 0.3