SI53102-A1 Datasheet, PDF (7/15 Pages) Silicon Laboratories – PCI-EXPRESS GEN 1, GEN 2, GEN 3, AND GEN 4 1:2 FAN-OUT CLOCK BUFFER

Si53102-A1/A2/A3
2. Test and Measurement Setup
Figures 1 through 3 show the test load configuration for the differential clock signals.
OUT+
OUT-
L1 = 5"
L1
50
L1
50
M easurem ent
P oint
2 pF
M easurem ent
P oint
2 pF
Figure 1. 0.7 V Differential Load Configuration
The outputs from this device can also support LVDS, LVPECL, or CML differential signaling levels using alternative
termination. For recommendations on how to achieve this, see “AN781: Alternative Output Termination for
Si5213x, Si5214x, Si5121x, and Si5315x PCIe Clock Generator and Buffer Families” at www.silabs.com.
Figure 2. Differential Measurement for Differential Output Signals
(AC Parameters Measurement)
Rev 1.2
7