SI53102-A1 Datasheet, PDF (13/15 Pages) Silicon Laboratories – PCI-EXPRESS GEN 1, GEN 2, GEN 3, AND GEN 4 1:2 FAN-OUT CLOCK BUFFER

7. PCB Land Pattern
Si53102-A1/A2/A3
Figure 7. Si53102 8-Pin TDFN Land Pattern
Table 8. Si53102 8-Pin Land Pattern Dimensions
Dimension
mm
C
1.40
E
0.40
X1
0.75
Y1
0.20
X2
0.25
Y2
1.10
Notes:
General
1. All dimensions shown are in millimeters (mm).
2. This Land Pattern Design is based on the IPC-7351 guidelines.
3. All dimensions shown are at Maximum Material Condition (MMC). Least
Material Condition (LMC) is calculated based on a Fabrication Allowance of
0.05 mm.
Solder Mask Design
4. All metal pads are to be non-solder mask defined (NSMD). Clearance
between the solder mask and the metal pad is to be 60 µm minimum, all the
way around the pad.
Stencil Design
5. A stainless steel, laser-cut and electro-polished stencil with trapezoidal
walls should be used to assure good solder paste release.
6. The stencil thickness should be 0.125 mm (5 mils).
7. The ratio of stencil aperture to land pad size should be 1:1 for all pads.
Card Assembly
8. A No-Clean, Type-3 solder paste is recommended.
9. The recommended card reflow profile is per the JEDEC/IPC J-STD-020
specification for Small Body Components.
Rev 1.2
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