SI4460-C2A-GM Datasheet, PDF (7/53 Pages) Silicon Laboratories – HIGH-PERFORMANCE, LOW-CURRENT TRANSCEIVER

Si4463/61/60-C
Table 3. Receiver AC Electrical Characteristics^1,2 (Continued)
Parameter
RX Sensitivity
915/868 MHz³
RX Channel Bandwidth
RSSI Resolution
1-Ch Offset Selectivity,
169 MHz³
1-Ch Offset Selectivity,
450 MHz³
1-Ch Offset Selectivity,
868 / 915 MHz³
Blocking 1 MHz Offset
Blocking 8 MHz Offset
Symbol
Test Condition
Min
P_{RX_0.5}
(BER < 0.1%)
—
(500 bps, GFSK, BT = 0.5,
f = 250Hz)
P_{RX_40}
(BER < 0.1%)
—
(40 kbps, GFSK, BT = 0.5,
f = 20 kHz)
P_{RX_100}
(BER < 0.1%)
—
(100 kbps, GFSK, BT = 0.5,
f = 50 kHz)
P_{RX_500}
(BER < 0.1%)
—
(500 kbps, GFSK, BT = 0.5,
f = 250 kHz)
P_{RX_9.6}
(PER 1%)
—
(9.6 kbps, 4GFSK, BT = 0.5,
f =  kHz)
P_{RX_1M}
(PER 1%)
—
(1 Mbps, 4GFSK, BT = 0.5,
inner deviation = 83.3 kHz)
P_{RX_OOK} (BER < 0.1%, 4.8 kbps, 350 kHz BW, —
OOK, PN15 data)
(BER < 0.1%, 40 kbps, 350 kHz BW, —
OOK, PN15 data)
(BER < 0.1%, 120 kbps, 350 kHz BW, —
OOK, PN15 data)
BW
1.1
RES_RSSI
Valid from –110 dBm to –90 dBm
—
C/I_1-CH Desired Ref Signal 3 dB above sensitiv- —
ity, BER < 0.1%. Interferer is CW, and
C/I_1-CH
desired is modulated with 2.4 kbps
F = 1.2 kHz GFSK with BT = 0.5, RX
—
channel BW = 4.8 kHz,
C/I_1-CH
channel spacing = 12.5 kHz
—
1M_BLOCK Desired Ref Signal 3 dB above sensitiv- —
8M_BLOCK
ity, BER = 0.1%. Interferer is CW, and
desired is modulated with 2.4 kbps,
—
F = 1.2 kHz GFSK with BT = 0.5,
RX channel BW = 4.8 kHz
Typ Max Unit
–127 — dBm
–109 –107 dBm
–104 –102 dBm
–97 –92 dBm
–109 — dBm
–88 — dBm
–108 –104 dBm
–101 –97 dBm
–96 –91 dBm
— 850 kHz
±0.5 —
dB
–69 –59 dB
–60 –50 dB
–55 –45 dB
–79 –68 dB
–86 –75 dB
Notes:
1. All minimum and maximum values are guaranteed across the recommended operating conditions of supply voltage and
from –40 to +85 °C unless otherwise stated. All typical values apply at VDD = 3.3 V and 25 °C unless otherwise stated.
2. For PER tests, 48 preamble symbols, 4 byte sync word, 10 byte payload and CRC-32 was used.
3. Measured over 50000 bits using PN9 data sequence and data and clock on GPIOs. Sensitivity is expected to be better
if reading data from packet handler FIFO especially at higher data rates.
Rev 1.0
7