SI4460-C2A-GM Datasheet, PDF (23/53 Pages) Silicon Laboratories – HIGH-PERFORMANCE, LOW-CURRENT TRANSCEIVER

Si4463/61/60-C
3.6. GPIO
Four general purpose IO pins are available to utilize in the application. The GPIO are configured by the
GPIO_PIN_CFG command in address 13h. For a complete list of the GPIO options please see the API guide.
GPIO pins 0 and 1 should be used for active signals such as data or clock. GPIO pins 2 and 3 have more
susceptibility to generating spurious in the synthesizer than pins 0 and 1. The drive strength of the GPIOs can be
adjusted with the GEN_CONFIG parameter in the GPIO_PIN_CFG command. By default the drive strength is set
to minimum. The default configuration for the GPIOs and the state during SDN is shown below in Table 12.The
state of the IO during shutdown is also shown inTable 12. As indicated previously in Table 6, GPIO 0 has lower
drive strength than the other GPIOs.
Table 12. GPIOs
Pin
GPIO0
GPIO1
GPIO2
GPIO3
nIRQ
SDO
SDI
SCLK
NSEL
SDN State
0
0
0
0
resistive VDD pull-up
resistive VDD pull-up
High Z
High Z
High Z
POR Default
POR
CTS
POR
POR
nIRQ
SDO
SDI
SCLK
NSEL
Rev 1.0
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