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C8051F340_0608 Datasheet, PDF (65/288 Pages) Silicon Laboratories – Full Speed USB Flash MCU Family | |||
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C8051F340/1/2/3/4/5/6/7
CP0+
VIN+
VIN- CP0-
+
CP0
_
OUT
CIRCUIT CONFIGURATION
Positive Hysteresis Voltage
(Programmed with CP0HYP Bits)
VIN-
INPUTS
VIN+
Negative Hysteresis Voltage
(Programmed by CP0HYN Bits)
VOH
OUTPUT
VOL
Positive Hysteresis
Disabled
Negative Hysteresis
Disabled
Maximum
Positive Hysteresis
Maximum
Negative Hysteresis
Figure 7.2. Comparator Hysteresis Plot
Comparator hysteresis is programmed using Bits3-0 in the Comparator Control Register CPTnCN (shown
in SFR Definition 7.1 and SFR Definition 7.4). The amount of negative hysteresis voltage is determined by
the settings of the CPnHYN bits. As shown in Figure 7.2, various levels of negative hysteresis can be
programmed, or negative hysteresis can be disabled. In a similar way, the amount of positive hysteresis is
determined by the setting the CPnHYP bits.
Comparator interrupts can be generated on both rising-edge and falling-edge output transitions. (For Inter-
rupt enable and priority control, see Section â9.3. Interrupt Handlerâ on page 91.) The CPnFIF flag is set
to â1â upon a Comparator falling-edge, and the CPnRIF flag is set to â1â upon the Comparator rising-edge.
Once set, these bits remain set until cleared by software. The output state of the Comparator can be
obtained at any time by reading the CPnOUT bit. The Comparator is enabled by setting the CPnEN bit to
â1â, and is disabled by clearing this bit to â0â.
Rev. 1.0
65
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