C8051F340_0608 Datasheet, PDF (11/288 Pages) Silicon Laboratories – Full Speed USB Flash MCU Family

C8051F340/1/2/3/4/5/6/7
Figure 19.2. UART1 Timing Without Parity or Extra Bit.......................................... 225
Figure 19.3. UART1 Timing With Parity ................................................................. 225
Figure 19.4. UART1 Timing With Extra Bit ............................................................. 225
Figure 19.5. Typical UART Interconnect Diagram.................................................. 226
Figure 19.6. UART Multi-Processor Mode Interconnect Diagram .......................... 227
20. Enhanced Serial Peripheral Interface (SPI0)
Figure 20.1. SPI Block Diagram ............................................................................. 233
Figure 20.2. Multiple-Master Mode Connection Diagram ....................................... 236
Figure 20.3. 3-Wire Single Master and Slave Mode Connection Diagram ............. 236
Figure 20.4. 4-Wire Single Master Mode and Slave Mode Connection Diagram ... 236
Figure 20.5. Master Mode Data/Clock Timing ........................................................ 238
Figure 20.6. Slave Mode Data/Clock Timing (CKPHA = 0) .................................... 239
Figure 20.7. Slave Mode Data/Clock Timing (CKPHA = 1) .................................... 239
Figure 20.8. SPI Master Timing (CKPHA = 0)........................................................ 243
Figure 20.9. SPI Master Timing (CKPHA = 1)........................................................ 243
Figure 20.10. SPI Slave Timing (CKPHA = 0)........................................................ 244
Figure 20.11. SPI Slave Timing (CKPHA = 1)........................................................ 244
21. Timers
Figure 21.1. T0 Mode 0 Block Diagram.................................................................. 248
Figure 21.2. T0 Mode 2 Block Diagram.................................................................. 249
Figure 21.3. T0 Mode 3 Block Diagram.................................................................. 250
Figure 21.4. Timer 2 16-Bit Mode Block Diagram .................................................. 255
Figure 21.5. Timer 2 8-Bit Mode Block Diagram .................................................... 256
Figure 21.6. Timer 2 Capture Mode (T2SPLIT = ‘0’) .............................................. 257
Figure 21.7. Timer 2 Capture Mode (T2SPLIT = ‘1’) .............................................. 258
Figure 21.8. Timer 3 16-Bit Mode Block Diagram .................................................. 261
Figure 21.9. Timer 3 8-Bit Mode Block Diagram .................................................... 262
Figure 21.10. Timer 3 Capture Mode (T3SPLIT = ‘0’) ............................................ 263
Figure 21.11. Timer 3 Capture Mode (T3SPLIT = ‘1’) ............................................ 264
22. Programmable Counter Array (PCA0)
Figure 22.1. PCA Block Diagram............................................................................ 267
Figure 22.2. PCA Counter/Timer Block Diagram.................................................... 268
Figure 22.3. PCA Interrupt Block Diagram ............................................................. 269
Figure 22.4. PCA Capture Mode Diagram.............................................................. 270
Figure 22.5. PCA Software Timer Mode Diagram .................................................. 271
Figure 22.6. PCA High Speed Output Mode Diagram............................................ 272
Figure 22.7. PCA Frequency Output Mode ............................................................ 273
Figure 22.8. PCA 8-Bit PWM Mode Diagram ......................................................... 274
Figure 22.9. PCA 16-Bit PWM Mode...................................................................... 275
Figure 22.10. PCA Module 4 with Watchdog Timer Enabled ................................. 276
23. C2 Interface
Figure 23.1. Typical C2 Pin Sharing....................................................................... 285
Rev. 1.0
11