SI5350B-B Datasheet, PDF (6/32 Pages) Silicon Laboratories – FACTORY-PROGRAMMABLE ANY-FREQUENCY CMOS CLOCK GENERATOR

Si5350B-B
Table 6. Output Characteristics
(V_DD = 2.5 V ±10%, or 3.3 V ±10%, T_A = –40 to 85 °C)
Parameter
Frequency Range¹
Load Capacitance
Duty Cycle
Rise/Fall Time
Output High Voltage
Output Low Voltage
Symbol
FCLK
C_L
DC
t_r/t_f
VOH
VOL
Test Condition
Min
Typ
0.0025
—
F_CLK < 100 MHz
—
—
F_CLK  160 MHz, measured
at VDD/2
45
50
F_CLK  160 MHz, measured
at VDD/2
40
50
20% - 80%, C_L = 5 pF
—
1
V_DD – 0.6 —
—
—
Max
200
15
55
60
1.5
—
0.6
Units
MHz
pF
%
%
ns
V
V
Period Jitter^2,3
20-QFN, 4 outputs running,
1 per VDDO
—
JPER
10-MSOP or 20-QFN,
all outputs running
—
40
95
ps pk-pk
70
155
Cycle-to-Cycle Jitter^2,3
JCC
20‐QFN, 4 outputs running, 1
—
per VDDO
10-MSOP or 20-QFN,
all outputs running
—
50
90
ps pk
70
150
20-QFN, 4 outputs running,
Period Jitter, VCXO^2,3 JPER_VCXO
1 per VDDO
—
10-MSOP or 20-QFN,
all outputs running
—
50
95
ps pk-pk
70
155
Cycle-to-Cycle Jitter,
VCXO^2,3
JCC_VCXO
20-QFN, 4 outputs running,
1 per VDDO
10-MSOP or 20-QFN,
all outputs running
—
—
50
90
ps pk
70
150
Notes:
1. Only two unique frequencies above 112.5 MHz can be simultaneously output.
2. Measured over 10k cycles. Jitter is only specified at the default high drive strength (50  output impedance).
3. Jitter is highly dependent on device frequency configuration. Specifications represent a “worst case, real world”
frequency plan; actual performance may be substantially better. Three-output 10MSOP package measured with clock
outputs of 74.25, 24.576, and 48 MHz. Eight-output 20QFN package measured with clock outputs of 33.33, 74.25, 27,
24.576, 22.5792, 28.322, 125, and 48 MHz.
6
Rev. 1.0