SI5350B-B Datasheet, PDF (15/32 Pages) Silicon Laboratories – FACTORY-PROGRAMMABLE ANY-FREQUENCY CMOS CLOCK GENERATOR

Si5350B-B
4.3.4. Output Enable (OEB_0, OEB_1, OEB_2)
Up to three output enable pins (OEB_0/1/2) are available on the Si5350B. Similar to the FS pins, each OEB pin can
be linked to any of the output clocks. In the example shown in Figure 9, OEB_0 is linked to control CLK0, CLK3,
and CLK5; OEB_1 is linked to control CLK6 and CLK7, and OEB_2 is linked to control CLK1, CLK2, CLK4, and
CLK5. Any other combination is also possible. If more than one OEB pin is linked to the same CLK output, the pin
forcing a disable state will be dominant. Clock outputs are enabled when the OEB pin is held low.
The output enable control circuitry ensures glitchless operation by starting the output clock cycle on the first leading
edge after OEB is asserted (OEB = low). When OEB is released (OEB = high), the clock is allowed to complete its
full clock cycle before going into a disabled state. This is shown in Figure 9. When disabled, the output state is
configurable as disabled high, disabled low, or disabled in high-impedance.
OEB_0
0
1
Output State
CLK Enabled
CLK Disabled
OEB_1
0
1
Output State
CLK Enabled
CLK Disabled
OEB_2
0
1
Output State
CLK Enabled
CLK Disabled
Customizable OEB Control
OEB_0
OEB_1
OEB_2
CLK0
OEB
CLK1
OEB
CLK2
OEB
CLK3
OEB
CLK4
OEB
CLK5
OEB
CLK6
OEB
CLK7
OEB
Glitchless Output Enable
CLKx
OEBx
Clock starts on the
first leading edge
Clock continues until
cycle is complete
Figure 9. Example Configuration of a Pin-Controlled Output Enable
Rev. 1.0
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