SI5350B-B Datasheet, PDF (16/32 Pages) Silicon Laboratories – FACTORY-PROGRAMMABLE ANY-FREQUENCY CMOS CLOCK GENERATOR

Si5350B-B
4.4. Voltage Control Input (VC)
The VCXO architecture of the Si5350B eliminates the need for an external pullable crystal. Only a standard, low-
cost, fixed-frequency (25 or 27 MHz) AT-cut crystal is required.
The tuning range of the VCXO is configurable allowing for a wide variety of applications. Key advantages of the
VCXO design in the Si5350B include high linearity, a wide operating range (linear from 10 to 90% of VDD), and
reliable startup and operation. Refer to Table 4 on page 5 for VCXO specification details.
A unique feature of the Si5350B is its ability to generate multiple output frequencies controlled by the same control
voltage applied to the VC pin. This replaces multiple PLLs or VCXOs that would normally be locked to the same
reference. An example is illustrated in Figure 10.
Fixed Frequency
XA
XB _{Crystal (non-pullable)}
Control ^VC
Voltage
OSC
VCXO
Multi
Synth
R0
0
Multi
Synth
R1
1
Multi
Synth
R2
2
CLK0
CLK1
CLK2
The clock frequency
generated from CLK0 is
controlled by the VC input
Additional MultiSynths
can be “linked” to the
VCXO to generate
additional clock
frequencies
Figure 10. Using the Si5350B as a Multi-Output VCXO
4.4.1. Control Voltage Gain (kV)
The voltage level on the VC pin directly controls the output frequency. The rate of change in output clock frequency
(kv) is configurable from 18 ppm/V up to 150 ppm/V. This allows a configurable pull range from ±30 ppm to
±240 ppm @ V_DD = 3.3 V as shown in Figure 11. Consult the factory for other pull range values.
A key advantage of the VCXO design in the Si5350B is its highly linear tuning range. This allows better control of
PLL stability and jitter performance over the entire control voltage range.
Pull-in Range
@ V_DD = 3.3 V
1000
750
500
250
10
0
-10
-250
kv ^{= 250 ppm/V}
kv ^{= 150 ppm/V}
kv = 6 ^ppm/V
VDD
2
VDD
-500
-750
-1000
VC (Volts)
Figure 11. User-definable VCXO Pull Range
16
Rev. 1.0