SI8900 Datasheet, PDF (5/32 Pages) Silicon Laboratories – ISOLATED MONITORING ADC

Si8900/1/2
Table 2. Electrical Specifications (Continued)
Parameter
Symbol
Test Condition
Min
Typ
Reset and Undervoltage Lockout
Power-on RESET
Voltage Threshold High
VRSTH
—
—
Power-on RESET
Voltage Threshold Low
VRSTL
1.7
—
VDDA Power-On Reset Ramp tRAMP Time from VDDA = 0 V
—
—
Time
to VDDA > VRST
Power-On Reset
Delay Time
Output Side UVLO Threshold
tPOR
UVLO
tRAMP < 1 ms
—
2.3
Output side UVLO
H
Hysteresis
Digital Inputs
—
100
Logic High Level Input Voltage
V_IH
Logic Low Level Input Voltage
V_IL
Logic Input Current
I_IN
Input Capacitance
C_IN
Digital Outputs
0.7 x V_DDB
—
—
—
VIN = 0 V or V_DD
–10
—
15
Logic High Level Output Voltage V_OH
Logic Low Level Output Voltage V_OL
Digital Output Series Impedance
Serial Ports
R_OUT
V_DDB = 5 V,
I_OH = –4 mA
V_DDB–0.4
4.8
V_DDB = 3.3 V,
I_OH = –4 mA
3.1
—
V_DDB = 3.3 to 5 V,
—
0.2
I_OL = 4 mA
—
85
UART Bit Rate
SMBus/I²C Bit Rate
60
—
Slave
—
—
Address = 1111000x
SPI Port
—
—
Max Unit
1.8
V
—
V
1
ms
0.3
ms
—
V
—
mV
—
V
0.6
V
+10
µA
—
pF
—
V
—
V
0.4
V
—

234
kbps
240
kbps
2.5
Mbps
Rev. 1.1
5