SI8900 Datasheet, PDF (10/32 Pages) Silicon Laboratories – ISOLATED MONITORING ADC

Si8900/1/2
3. Functional Description
The Si8900/1/2 (Figure 4) are isolated monitoring ADCs that convert linear input signals into digital format and
transmit the resulting data through an on-chip isolated serial port to an external master processor (typically a
microcontroller). The Si890x access protocol is simple: The master configures and controls the start of ADC
conversion by writing a configuration register (CNFG_0) Command Byte to the Si890x. The master then acquires
ADC conversion data by reading the Si890x serial port. Devices in this series differ only in the type of serial port.
Options include a UART with on-chip baud rate generator that operates at 234 kbps max (Si8900), an SMBus/I²C
port that operates at 240 kbps max (Si8901), and an SPI Port that operates at 2.5 MHz max (Si8902).
The integrated ADC subsystem consists of a three-channel analog input multiplexer (MUX) followed by a series
gain amplifier (selectable 1x or 0.5x gain) and 10-bit SAR ADC. Serial-port-accessible ADC options allow the user
to select an internal or external voltage reference, set the programmable gain amplifier (PGA), and select the ADC
MUX address. The master can configure the Si890x to return ADC data on-demand (Demand Mode) or
continuously (Burst Mode). For more information, see "CNFG_0 Command Byte" on page 18.
VDDA
AIN0
AIN1
AIN2
VREF
RST
GNDA
MUX PGA
10‐Bit
ADC
Tx Data _UART
VREF
ADC Subsystem
All
Blocks
State Machine/
User Registers
Si8900
ISOLATION
VDDB
Tx
Rx
GNDB
VDDA
AIN0
AIN1
AIN2
VREF
RST
RSDA
GNDA
MUX PGA
10‐Bit Tx Data SMBus/
ADC
I²C
VREF
ADC Subsystem
All
Blocks
State Machine/
User Registers
Si8901
ISOLATION
VDDB
SDA
SCL
GNDB
VDDA
AIN0
AIN1
AIN2
VREF
RST
GND1
MUX PGA
10‐Bit
ADC
Tx Data
SPI Port
VREF
ADC Subsystem
All
Blocks
State Machine/
User Registers
ISOLATION
Si8902
Figure 4. Si8900/1/2 Block Diagrams
VDDB
SCK
SDI
SDO
EN
GND2
10
Rev. 1.1