SI8900 Datasheet, PDF (14/32 Pages) Silicon Laboratories – ISOLATED MONITORING ADC

Si8900/1/2
4.2. I²C/SMBus (Si8901)
The I²C/SMBus serial port is a two-wire serial bus where data line SDA is bidirectional and clock line SCL is
unidirectional. Reads and writes to this interface by the master are byte-oriented, with the I²C/SMBus master
controlling the serial data rates up to 240 kbps. The SDA and SCL lines must be pulled high through pull-up
resistors of 5 k or less. An Si8901 ADC read transaction begins with a START condition (“S” or Repeated START
condition “SR”), which is defined as a high-to-low transition on SDA while SCL is high (Figure 9). The master
terminates a transmission with a STOP condition (P), defined as a low-to-high transition on SDA while SCL is high.
The data on SDA must remain stable during the high period of the SCL clock pulse because such changes in either
line will be interpreted as a control command (e.g., S, P SR). SDA and SCL idle in the high state when the bus is
not busy. Acknowledge bits (Figure 10) provide detection of successful data transfers, whereas unsuccessful
transfers conclude with a not-acknowledge bit (NACK). Both the master and the Si8901 generate ACK and NACK
bits. An ACK bit is generated when the receiving device pulls SDA low before the rising edge of the acknowledged
related (ninth) SCL pulse and maintains it low during the high period of the clock pulse. A NACK bit is generated
when the receiver allows SDA to be pulled high before the rising edge of the acknowledged related SCL pulse and
maintains it high during the high period of the clock pulse. An unsuccessful data transfer occurs if a receiving
device is busy or if a system fault has occurred. In the event of an unsuccessful data transfer, the bus master
attempts communication at a later time. Figure 11A shows the I²C Slave Address Byte and CNFG_0 byte for the
Si8901. Figure 11B and Figure 11C show master/Si8901 ADC read transactions for Demand Mode and Burst
Mode, respectively.
S
S_R
P
SDA
SCL
SDA
SCL
Figure 9. Start and Stop Conditions
S
Not Acknowledge (NACK)
1
2
Acknowledge (ACK)
9
Figure 10. Acknowledge Cycle
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Rev. 1.1