SI8900 Datasheet, PDF (18/32 Pages) Silicon Laboratories – ISOLATED MONITORING ADC

Si8900/1/2
5. Si8900/1/2 Configuration Registers
CNFG_0 Command Byte
Bit
D7
Name
1
Type
R/W
Default
1
D6
1
R/W
1
D5
MX1
R/W
1
D4
MX0
R/W
1
D3
VREF
R/W
1
D2
—
R/W
1
D1
MODE
R/W
1
Bit
Name
Function
7:6
1,1
Internal use. These bits are always set to 1.
5:4
MX1, MX0 ADC MUX Address.
ADC MUX address selection is controlled by MX1, MX0 as follows:
D0
PGA
R/W
1
MX1
1
1
0
0
MX0
1
0
1
0
Selected ADC MUX Channel
Not Used
AIN2
AIN1
AIN0
3
VREF ADC Voltage Reference Source
VDD is selected as the reference voltage when this bit is set to 1. An externally con-
nected voltage reference generator is selected when this bit is reset to 0.
2
—
Not used.
1
MODE ADC Read Mode
ADC Demand Mode read is enabled when this bit is 1, and Burst Mode is enabled
when this bit is 0. For more information on Demand and Burst mode operation,
please see "ADC Data Transmission Modes" on page 11.
0
PGA
PGA Gain Set
PGA gain is 1 when this bit is set to 1. PGA gain is 0.5 when this bit is reset to 0.
18
Rev. 1.1