SI8900 Datasheet, PDF (11/32 Pages) Silicon Laboratories – ISOLATED MONITORING ADC

Si8900/1/2
4. ADC Data Transmission Modes
The master can access ADC read-only registers ADC_H and ADC_L using either Demand Mode or Burst Mode. In
Demand Mode (MODE = 1), the master triggers individual A/D conversions “on-demand”. In Burst Mode
(MODE = 0), the Si890x performs ADC conversions continuously.
Master to Slave
Slave to Master
Master writes CNFG_0
Command Byte to Si8900 Rx
CNFG_0
Command
Byte
MODE = 1
tCONV
CNFG_0
Command
Byte
ADC_H
ADC_L
Master reads updated CNFG_0 and ADC
Data From Si8900 (Tx output)
B) Si8900 Demand Mode ADC Read
Master to Slave
Slave to Master
Master writes Slave Address and
CNFG_0 Command Byte to Si8901 SDA
Slave Address
CNFG_0
Command
Byte
Slave
Address
MODE = 1
tCONV
CNFG_0
Command
Byte
ADC_H
ADC_L
Master reads Slave Address, updated CNFG_0
and ADC Data from Si8901 (SDA pin)
C) Si8901 Demand Mode ADC Read
Master to Slave
Slave to Master
Master writes CNFG_0
Command Byte to Si8902 SDI
The master must wait 8µS
(track‐and‐hold time) before
reading ADC data packet.
CNFG_0
Command
Byte
tCONV
MODE = 1
CNFG_0
Command
Byte
ADC_H
ADC_L
Master reads updated CNFG_0 and
ADC Data from Si8902 SDO
D) Si8902 Demand Mode ADC Read
Figure 5. ADC Demand Mode Operation
Referring to Figure 5A, a Demand Mode ADC read is initiated when the master writes a Command Byte to the
Si8900. (The Command Byte is a copy of the CNFG_0 register that has been properly configured by the master.)
Upon receipt of the Command Byte, the Si8900 updates its CNFG_0 register and triggers the start of an ADC
conversion, at which time the master may immediately begin reading ADC conversion data from the Si8900 UART.
The ADC conversion data packet contains a copy of the Command Byte for verification and two-bytes of ADC
conversion data. The Si8901 (Figure 5B) ADC read transaction is identical to that of the Si8900 with the exception
of the added I²C/SMBus Slave Address byte (Si8901 Slave Address is 0xF0). The Si8902 Demand Mode ADC
read transaction (Figure 5C) is the same as that of the Si8900, except the master must wait 8 µs after the
transmission of the Command Byte before reading the Si8902 SPI port because byte transmission time is two
times shorter versus the Si8900/01.
Rev. 1.1
11