SI550 Datasheet, PDF (5/12 Pages) Silicon Laboratories – VOLTAGE-CONTROLLED CRYSTAL OSCILLATOR (VCXO) 10 MHZ TO 1.4 GHZ

Si550
Table 6. CLK± Output Period Jitter
Parameter
Symbol
Test Condition
Min
Period Jitter*
for F_OUT < 160 MHz
J_PER
RMS
—
Peak-to-Peak
—
*Note: Any output mode, including CMOS, LVPECL, LVDS, CML. N = 1000 cycles.
Table 7. CLK± Output Phase Noise (Typical)
Configuration
Offest Frequency (f)
100 Hz
1 kHz
10 kHz
100 kHz
1 MHz
10 MHz
100 MHz
f_C
K_V
Output
74.25 MHz
45 ppm/V
CMOS
300 MHz
90 ppm/V
LVPECL
L (f)
–94
–117
–128
–135
–138
–143
n/a
–74
–98
–112
–122
–134
–144
–147
Typ
Max Units
2
—
ps
14
—
622.08 MHz
45 ppm/V
LVPECL
Units
–77
–101
–114
–118
–128
–144
–147
dBc/Hz
Preliminary Rev. 0.3
5