SI550 Datasheet, PDF (4/12 Pages) Silicon Laboratories – VOLTAGE-CONTROLLED CRYSTAL OSCILLATOR (VCXO) 10 MHZ TO 1.4 GHZ

Si550
Table 4. CLK± Output Levels and Symmetry (Continued)
Parameter
Symbol
Test Condition
Min
Typ
Max Units
Symmetry (duty cycle)
SYM LVPECL: V_DD – 1.3 V (diff)
LVDS: 1.25 V (diff)
45
—
55
%
CMOS: V_DD/2
Notes:
1. 50 Ω to V_DD – 2.0 V.
2. R_term = 100 Ω (differential).
3. C_L = 15 pF
Table 5. CLK± Output Phase Jitter
Parameter
Phase Jitter (RMS)^1,2,3
for F_OUT > 500 MHz
Symbol
Test Condition
Min
φ_J Kv = 45 ppm/V
12 kHz to 20 MHz (OC-48) —
50 kHz to 80 MHz (OC-192) —
Typ
0.35
0.38
Max Units
ps
—
—
Kv = 90 ppm/V
12 kHz to 20 MHz (OC-48) —
0.43
—
50 kHz to 80 MHz (OC-192) —
0.41
—
Kv = 135 ppm/V
12 kHz to 20 MHz (OC-48) —
0.52
—
50 kHz to 80 MHz (OC-192) —
0.46
—
Phase Jitter (RMS)^1,2,3
for F_OUT of 125 to 500 MHz
Kv = 180 ppm/V
12 kHz to 20 MHz (OC-48) —
0.64
—
50 kHz to 80 MHz (OC-192) —
0.52
—
φ_J Kv = 45 ppm/V
ps
12 kHz to 20 MHz (OC-48) —
0.42
—
50 kHz to 80 MHz (OC-192) —
0.58
—
Kv = 90 ppm/V
12 kHz to 20 MHz (OC-48) —
0.48
—
50 kHz to 80 MHz (OC-192) —
0.60
—
Kv = 135 ppm/V
12 kHz to 20 MHz (OC-48) —
0.57
—
50 kHz to 80 MHz (OC-192) —
0.64
—
Kv = 180 ppm/V
12 kHz to 20 MHz (OC-48) —
0.67
—
50 kHz to 80 MHz (OC-192) —
0.68
—
Notes:
1. Differential Modes: LVPECL/LVDS/CML. Refer to AN255, AN256, and AN266 for further information.
2. For best jitter and phase noise performance, always choose the smallest K_V that meets the application’s minimum APR
requirements. See “AN266: VCXO Tuning Slope (K_V), Stability, and Absolute Pull Range (APR)” for more information.
3. See “AN255: Replacing 622 MHz VCSO devices with the Si550 VCXO” for comparison highlighting power supply
rejection (PSR) advantage of Si55x versus SAW-based solutions.
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Preliminary Rev. 0.3