EFM8SB2 Datasheet, PDF (5/49 Pages) Silicon Laboratories – The EFM8SB2 highlighted features are listed below

3. System Overview
3.1 Introduction
EFM8SB2 Data Sheet
System Overview
C2CK/RSTb
Power On
Reset/PMU
Wake
Reset
Debug /
Programming
Hardware
CIP-51 8051 Controller
Core
64/32/16 KB ISP Flash
Program Memory
256 Byte SRAM
4096 Byte XRAM
C2D
VDD
Power Net
Analog
Power
VREG
Digital
Power
SYSCLK
GND
System Clock
SFR
Configuration
Bus
Precision
24.5 MHz
Oscillator
Port I/O Configuration
Digital Peripherals
UART
Timers 0,
1, 2, 3
PCA/WDT
SMBus
SPI 0,1
CRC
Priority
Crossbar
Decoder
Crossbar Control
External Memory Interface
Control
Address
Data
Port 0
Drivers
Port 1
Drivers
Port 2
Drivers
XTAL3
XTAL4
XTAL1
XTAL2
Low Power
20 MHz
Oscillator
External
Oscillator
Circuit
RTC
Oscillator
Analog Peripherals
Internal External
VREF VREF
10-bit
300ksps
ADC
Comparators
VDD
VREF
+-+-
Temp
Sensor
6-bit
IREF
IREF0
GND
Figure 3.1. Detailed EFM8SB2 Block Diagram
P0.n
P1.n
P2.n
silabs.com | Smart. Connected. Energy-friendly.
Rev. 1.1 | 4