EFM8SB2 Datasheet, PDF (14/49 Pages) Silicon Laboratories – The EFM8SB2 highlighted features are listed below

EFM8SB2 Data Sheet
Electrical Specifications
Parameter
Symbol Conditions
Min
Typ
Max
Units
Note:
1. Based on device characterization data; Not production tested.
2. SYSCLK must be at least 32 kHz to enable debugging.
3. Digital Supply Current depends upon the particular code being executed. The values in this table are obtained with the CPU exe-
cuting an “sjmp $” loop, which is the compiled form of a while(1) loop in C. One iteration requires 3 CPU clock cycles, and the
flash memory is read on each cycle. The supply current will vary slightly based on the physical location of the sjmp instruction and
the number of flash address lines that toggle as a result. In the worst case, current can increase by up to 30% if the sjmp loop
straddles a 128-byte flash address boundary (e.g., 0x007F to 0x0080). Real-world code with larger loops and longer linear se-
quences will have few transitions across the 128-byte address boundaries.
4. Includes supply current from regulator and oscillator source (24.5 MHz high-frequency oscillator, 20 MHz low-power oscillator, or
32.768 kHz RTC oscillator).
5. IDD can be estimated for frequencies < 10 MHz by simply multiplying the frequency of interest by the frequency sensitivity num-
ber for that range, then adding an offset of 90 µA. When using these numbers to estimate I_DD for > 10 MHz, the estimate should
be the current at 25 MHz minus the difference in current indicated by the frequency sensitivity number. For example: V_DD = 3.0 V;
F = 20 MHz, I_DD = 4.1 mA – (25 MHz – 20 MHz) x 0.120 mA/MHz = 3.5 mA assuming the same oscillator setting.
6. Idle IDD can be estimated by taking the current at 25 MHz minus the difference in current indicated by the frequency sensitivity
number. For example: V_DD = 3.0 V; F = 5 MHz, Idle I_DD = 2.5 mA – (25 MHz – 5 MHz) x 0.095 mA/MHz = 0.6 mA.
7. ADC0 always-on power excludes internal reference supply current.
8. The internal reference is enabled as-needed when operating the ADC in burst mode to save power.
9. IREF0 supply current only. Does not include current sourced or sunk from IREF0 output pin.
Table 4.3. Reset and Supply Monitor
Parameter
Symbol Test Condition
Min
VDD Supply Monitor Threshold
V_VDDM
Reset Trigger
1.7
V_WARN
Early Warning
1.8
VDD Supply Monitor Turn-On Time t_MON
—
Power-On Reset (POR) Monitor
Threshold
V_POR
Initial Power-On (Rising Voltage on
—
V_DD)
Falling Voltage on V_DD
0.7
Brownout Recovery (Rising Volt-
—
age on V_DD)
V_DD Ramp Time
t_RMP
Time to V_DD ≥ 1.8 V
—
Reset Delay
t_RST
Time between release of reset
—
source and code execution
RST Low Time to Generate Reset t_RSTL
15
Missing Clock Detector Response t_MCD
F_SYSCLK > 1 MHz
100
Time (final rising edge to reset)
Missing Clock Detector Trigger
F_MCD
—
Frequency
Table 4.4. Flash Memory
Parameter
Symbol Test Condition
Min
Write Time¹
t_WRITE
One Byte
57
Erase Time¹
t_ERASE
One Page
28
Typ
Max
Unit
1.75
1.8
V
1.85
1.9
V
300
—
ns
0.75
—
V
0.8
0.9
V
0.95
—
V
—
3
ms
10
—
µs
—
—
µs
650
1000
µs
7
10
kHz
Typ
Max
Units
64
71
µs
32
36
ms
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