EFM8SB2 Datasheet, PDF (16/49 Pages) Silicon Laboratories – The EFM8SB2 highlighted features are listed below

Table 4.9. ADC
Parameter
Symbol Test Condition
Min
Resolution
N_bits
Throughput Rate
f_S
—
Tracking Time
t_TRK
1.5
Power-On Time
t_PWR
1.5
SAR Clock Frequency
f_SAR
High Speed Mode,
—
Conversion Time
T_CNV
13
Sample/Hold Capacitor
C_SAR
Gain = 1
—
Gain = 0.5
—
Input Pin Capacitance
C_IN
—
Input Mux Impedance
R_MUX
—
Voltage Reference Range
V_REF
1
Input Voltage Range¹
V_IN
Gain = 1
0
Gain = 0.5
0
Power Supply Rejection Ratio
PSRR_ADC Internal High Speed VREF
—
External VREF
—
DC Performance
Integral Nonlinearity
INL
—
Differential Nonlinearity (Guaran- DNL
—
teed Monotonic)
Offset Error
E_OFF
VREF = 1.65 V
–2
Offset Temperature Coefficient
TC_OFF
—
Slope Error
E_M
—
Dynamic Performance 10 kHz Sine Wave Input 1dB below full scale, Max throughput
Signal-to-Noise
SNR
54
Signal-to-Noise Plus Distortion
SNDR
54
Total Harmonic Distortion (Up to THD
—
5th Harmonic)
Spurious-Free Dynamic Range
SFDR
—
Note:
1. Absolute input pin voltage is limited by the V_DD supply.
EFM8SB2 Data Sheet
Electrical Specifications
Typ
Max
Unit
10
Bits
—
300
ksps
—
—
µs
—
—
µs
—
8.33
MHz
—
—
Clocks
30
—
pF
28
—
pF
20
—
pF
5
—
kΩ
—
V_DD
V
—
V_REF
V
—
2 x V_REF
V
67
—
dB
74
—
dB
±0.5
±0.5
0
0.004
±0.06
±1
±1
2
—
±0.24
LSB
LSB
LSB
LSB/°C
%
58
—
dB
58
—
dB
-73
—
dB
75
—
dB
Table 4.10. Voltage References
Parameter
Internal Fast Settling Reference
Output Voltage
Symbol Test Condition
V_REFFS
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Min
1.60
Typ
1.65
Max
Unit
1.70
V
Rev. 1.1 | 15