SI4706-C31 Datasheet, PDF (26/36 Pages) Silicon Laboratories – HIGH-PERFORMANCE FM RDS/RBDS RECEIVER

Si4706-C31
4.15.3. SPI Control Interface Mode
When selecting SPI mode, the user must ensure that a
rising edge of SCLK does not occur within 300 ns
before the rising edge of RST.
SPI bus mode uses the SCLK, SDIO, and SEN pins for
read/write operations. The system controller can
choose to receive read data from the device on either
SDIO or GPO1. A transaction begins when the system
controller drives SEN = 0. The system controller then
pulses SCLK eight times, while driving an 8-bit control
byte serially on SDIO. The device captures the data on
rising edges of SCLK. The control byte must have one
of five values:
 0x48 = write a command (controller drives 8
additional bytes on SDIO).
 0x80 = read a response (device drives one
additional byte on SDIO).
 0xC0 = read a response (device drives 16 additional
bytes on SDIO).
 0xA0 = read a response (device drives one
additional byte on GPO1).
 0xE0 = read a response (device drives 16 additional
bytes on GPO1).
For write operations, the system controller must drive
exactly eight data bytes (a command and seven
arguments) on SDIO after the control byte. The data is
captured by the device on the rising edge of SCLK.
For read operations, the controller must read exactly 1
byte (STATUS) after the control byte or exactly 16 data
bytes (STATUS and RESP1–RESP15) after the control
byte. The device changes the state of SDIO (or GPO1, if
specified) on the falling edge of SCLK. Data must be
captured by the system controller on the rising edge of
SCLK.
Keep SEN low until all bytes have transferred. A
transaction may be aborted at any time by setting SEN
high and toggling SCLK high and then low. Commands
will be ignored by the device if the transaction is
aborted.
For details on timing specifications and diagrams, refer
to Figure 6 and Figure 7 on page 10.
4.16. GPO Outputs
The Si4706 provides three general-purpose output pins.
The GPO pins can be configured to output a constant
low, constant high, or high-Z. The GPO pins are
multiplexed with the bus mode pins or DCLK,
depending on the application schematic of the device.
GPO2/INT can be configured to provide interrupts for
seek and tune complete, receive signal quality, and
RDS.
4.17. Reset, Powerup, and Powerdown
Setting the RST pin low will disable analog and digital
circuitry, reset the registers to their default settings, and
disable the bus. Setting the RST pin high will bring the
device out of reset. A powerdown mode is available to
reduce power consumption when the part is idle. Putting
the device in powerdown mode will disable analog and
digital circuitry while keeping the bus active.
4.18. Programming with Commands
To ease development time and offer maximum
customization, the Si4706 provides a simple yet
powerful software interface to program the receiver. The
device is programmed using commands, arguments,
properties, and responses. To perform an action, the
user writes a command byte and associated arguments,
causing the chip to execute the given command.
Commands control an action such as powerup the
device, shut down the device, or tune to a station.
Arguments are specific to a given command and are
used to modify the command. A complete list of
commands is available in “AN332: Si47xx Programming
Guide” and “AN344: Si4706/07/4x Programming
Guide.”
Properties are a special command argument used to
modify the default chip operation and are generally
configured immediately after powerup. Examples of
properties are de-emphasis level, RSSI seek threshold,
and soft mute attenuation threshold. Responses provide
the user information and are echoed after a command
and associated arguments are issued. All commands
provide a one-byte status update indicating interrupt
and clear-to-send status information. For a detailed
description of the commands and properties for the
Si4706, see “AN332: Si47xx Programming Guide” and
“AN344: Si4706/07/4x Programming Guide.”
26
Rev. 1.0