SI4706-C31 Datasheet, PDF (10/36 Pages) Silicon Laboratories – HIGH-PERFORMANCE FM RDS/RBDS RECEIVER

Si4706-C31
Table 7. SPI Control Interface Characteristics
(V_DD = 2.7 to 5.5 V, V_IO = 1.62 to 3.6 V, T_A = –20 to 85 °C)
Parameter
Symbol
Test Condition
Min
Typ
Max Unit
SCLK Frequency
f_CLK
0
—
2.5
MHz
SCLK High Time
t_HIGH
25
—
—
ns
SCLK Low Time
t_LOW
25
—
—
ns
SDIO Input, SEN to SCLKSetup
t_S
15
—
—
ns
SDIO Input to SCLKHold
SEN Input to SCLKHold
t_HSDIO
t_HSEN
10
—
—
ns
5
—
—
ns
SCLKto SDIO Output Valid
SCLKto SDIO Output High Z
t_CDV
t_CDZ
Read
Read
2
—
25
ns
2
—
25
ns
SCLK, SEN, SDIO, Rise/Fall time
t_R
t_F
—
—
10
ns
Note: When selecting SPI mode, the user must ensure that a rising edge of SCLK does not occur within 300 ns before the
rising edge of RST.
SCLK 70%
30%
SEN ^70%
30%
tS
tS
tR
tF
tHIGH tLOW
tHSDIO
tHSEN
SDIO 70%
30%
C7
C6–C1
C0
D7
D6–D1
D0
Control Byte In
8 Data Bytes In
Figure 6. SPI Control Interface Write Timing Parameters
SCLK 70%
30%
SEN 70%
30%
SDIO ^70%
30%
tS
tS
C7
C6–C1
tCDV
tHSDIO
C0
D7
tHSEN
D6–D1
tCDZ
D0
Control Byte In
Bus
Turnaround
16 Data Bytes Out
(SDIO or GPO1)
Figure 7. SPI Control Interface Read Timing Parameters
10
Rev. 1.0