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SI4706-C31 Datasheet, PDF (11/36 Pages) Silicon Laboratories – HIGH-PERFORMANCE FM RDS/RBDS RECEIVER | |||
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Si4706-C31
Table 8. Digital Audio Interface Characteristics
(VDD = 2.7 to 5.5 V, VIO = 1.62 to 3.6 V, TA = â20 to 85 °C)
Parameter
DCLK Cycle Time
DCLK Pulse Width High
DCLK Pulse Width Low
DFS Set-up Time to DCLK Rising Edge
DFS Hold Time from DCLK Rising Edge
DOUT Propagation Delay from DCLK Falling
Edge
Symbol Test Condition Min
tDCT
26
tDCH
10
tDCL
10
tSU:DFS
5
tHD:DFS
5
tPD:DOUT
0
Typ Max Unit
â 1000 ns
â
â
ns
â
â
ns
â
â
ns
â
â
ns
â
12
ns
DCLK
DFS
DOUT
tDCH
tDCL
tDCT
tHD:DFS
tSU:DFS
tPD:OUT
Figure 8. Digital Audio Interface Timing Parameters, I2S Mode
Rev. 1.0
11
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