SI4706-C31 Datasheet, PDF (22/36 Pages) Silicon Laboratories – HIGH-PERFORMANCE FM RDS/RBDS RECEIVER

Si4706-C31
4.12. Embedded Antenna Support
4.13. RDS Decoder
The Si4706 is the first FM receiver to support the fast
growing trend to integrate the FM receiver antenna into
the device enclosure. The chip is designed with this
function in mind from the outset, with multiple
international patents pending, thus it is superior to many
other options in price, board space, and performance.
Testing indicates that using Silicon Laboratories'
patented techniques, FM performance using an
embedded antenna can be very similar in many key
metrics to performance using standard half-wavelength
FM antennas. Refer to “AN383: Si47XX Antenna,
Schematic, Layout, And Design Guidelines” for
additional details on the implementation of support for
an embedded antenna.
Figure 14 shows a conceptual block diagram of the
Si4706 architecture used to support the embedded
antenna. The half-wavelength FM receive antenna is
therefore optional. Host software can detect the
presence of an external antenna and switch between
the embedded antenna if desired.
Half-wavelength
antenna
FMI
Integrated
antenna
LPI
RFGND
LNA
AGC
Si4706
Figure 14. Conceptual Block Diagram of the
Si4706 Embedded Antenna Support
The Si4706 implements an advanced, patented, high-
performance RDS processor for demodulation, symbol
decoding, block synchronization, error detection, and
error correction. The RDS decoder provides several
significant benefits over traditional implementations,
including very fast and robust RDS synchronization in
noisy signal levels with very high block error rates
(BLER), industry-leading sensitivity, and improved data
reliability in all signal environments.
Figure 15 illustrates the benefit of robust
synchronization. The Si4706's strong synchronization
performance at noisy signal levels minimizes or even
eliminates re-synchronization time required as the
signal carrier-to-noise ratio (CNR) fluctuates. The
Si4706 decoder is continuously synchronized to the
RDS block/group despite loss of data due to data block
errors. This translates to lower loss of data compared to
competing solutions.
Figure 16 illustrates the Si4706 RDS decoder
performance. With the aid of robust synchronization, the
decoder additionally provides for operation at lower
sensitivity levels for a given BLER compared to
competing solutions, and delivers reception in
environments where signal power is very low or
compromised. The decoder failure probability drops
significantly compared to competing solutions.
The Si4706 also provides unmatched flexibility in
programming the interaction between the host
processor and the device. The Si4706 can be
configured to provide varying levels of visibility from
very high visibility to each RDS block with
corresponding BLER, to a lower level of granularity
providing complete RDS groups with BLER by block.
Additionally, the Si4706 can provide interrupts on
changes to RDS block A and/or B. The Si4706 device
provides a configurable interrupt when RDS is
synchronized and RDS group data has been received.
The device provides configurable interrupts for up to
100 blocks with detailed BLER (25 groups), providing
flexibility in interrupt configuration to the host controller.
The Si4706 reports RDS decoder synchronization
status and detailed bit errors for each RDS block with
the FM_RDS_STATUS command. The range of
reportable bit errors that are detected and corrected are
0, 1-2, 3-5, and "not correctable." More than five bit
errors indicates that the corresponding block
information word is not correctable.
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Rev. 1.0