EFM8BB3 Datasheet, PDF (26/70 Pages) Silicon Laboratories – The EFM8BB3 device family are fully integrated, mixed-signal system-on-a-chip MCUs. Highlighted features are listed below

Parameter
Symbol Test Condition
Negative Hysteresis
Mode 3 (CPMD = 11)
HYS_CP-
CPHYN = 00
CPHYN = 01
CPHYN = 10
CPHYN = 11
Input Range (CP+ or CP-)
V_IN
Input Pin Capacitance
C_CP
Internal Reference DAC Resolution N_bits
Common-Mode Rejection Ratio
CMRR_CP
Power Supply Rejection Ratio
PSRR_CP
Input Offset Voltage
V_OFF
T_A = 25 °C
Input Offset Tempco
TC_OFF
Min
—
—
—
—
-0.25
—
—
—
-10
—
4.1.14 Configurable Logic
Table 4.14. Configurable Logic
Parameter
Symbol Test Condition
Min
Propagation Delay
t_DLY
Through single CLU
—
Clocking Frequency
F_CLK
1 or 2 CLUs Cascaded
—
3 or 4 CLUs Cascaded
—
EFM8BB3 Data Sheet
Electrical Specifications
Typ
Max
Unit
-1.5
—
mV
-4
—
mV
-8
—
mV
-16
—
mV
—
V_IO+0.25
V
7.5
—
pF
6
bits
70
—
dB
72
—
dB
0
10
mV
3.5
—
μV/°
Typ
Max
Unit
—
35.3
ns
—
73.5
MHz
—
36.75
MHz
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