SI53306 Datasheet, PDF (23/29 Pages) Silicon Laboratories – 1:4 LOW-JITTER UNIVERSAL BUFFER/LEVEL TRANSLATOR

Si53306
Table 20. Pin Description (Continued)
Pin
Name
9
Q2
Type*
O
Description
Output clock 2 (complement).
10
Q2
O
Output clock 2.
11
Q1
O
Output clock 1 (complement).
12
Q1
O
Output clock 1.
13
SFOUT0
14
Q0
I
Output signal format control pin 0.
Three-level input control. Internally biased at VDD/2. Can be
left floating or tied to ground or VDD.
O
Output clock 0 (complement).
15
Q0
O
Output clock 0.
16
OE
GND
Pad
GND
I
GND
Output enable.
When OE = high, all outputs are enabled.
When OE = low, Q is held low, and Q is held high for differen-
tial formats.
For LVCMOS, both Q and Q are held low when OE is set low.
OE contains an internal pull-up resistor.
Ground.
*Pin types are: I = input, O = output, P = power, GND = ground.
Rev. 1.0
23