SI53306 Datasheet, PDF (22/29 Pages) Silicon Laboratories – 1:4 LOW-JITTER UNIVERSAL BUFFER/LEVEL TRANSLATOR

Si53306
3. Pin Description: 16-Pin QFN
V_{DD 1}
CLK 2
CLK ³
GND 4
GND
PAD
12 Q1
11 _Q1
10 _Q2
9 _Q2
Pin
Name
1
VDD
2
CLK
3
CLK
4
GND
5
VDDO
6
Q3
7
Q3
8
SFOUT1
22
Table 20. Pin Description
Type*
P
I
Description
Core voltage supply.
Bypass with 1.0 μF capacitor and place as close to the VDD
pin as possible.
Input clock.
I
GND
P
O
Input clock (complement).
When the CLK is driven by a single-ended input, connect
CLK to VDD/2.
See Figure 1, “Differential Measurement Method Using a
Balun,” on page 9.
Ground.
Output voltage supply— All outputs (Q0 to Q3).
Bypass with 1.0 μF capacitor and place as close to the VDDO
pin as possible.
Output clock 3 (complement).
O
Output clock 3.
I
Output signal format control pin 1.
Three-level input control. Internally biased at VDD/2. Can be
left floating or tied to ground or VDD.
Rev. 1.0