SI53306 Datasheet, PDF (14/29 Pages) Silicon Laboratories – 1:4 LOW-JITTER UNIVERSAL BUFFER/LEVEL TRANSLATOR

Si53306
2.4. Synchronous Output Enable
This buffer features a synchronous output enable (disable) feature. Output enable is sampled and synchronized on
the falling edge of the input clock. This feature prevents runt pulses from being generated when the outputs are
enabled or disabled.
When OE is low, Q is held low and Q is held high for differential output formats. For LVCMOS output format
options, both Q and Q are held low when OE is set low. The device outputs are enabled when the output enable pin
is unconnected. See Table 10, “AC Characteristics,” on page 6 for output enable and output disable times.
2.5. Output Enable Logic
All four outputs are controlled with a single output enable (OE) pin. Table 18 summarizes the input and output clock
based upon the state of the input clock and the OE pin.
Table 18. Output Enable Logic
CLK
OE¹
Q²
L
H
L
H
H
H
X
L
L³
Notes:
1. Output enable active high
2. On the next negative transition of CLK.
3. Single-end: Q = low, Q = low
Differential: Q = low, Q = high
2.6. Power Supply (V_DD and V_DDO)
The buffer includes separate core (V_DD) and output driver supplies (V_DDOX). This feature allows the core to operate
at a lower voltage than V_DDO, reducing current consumption in mixed supply applications. The core V_DD supports
3.3 V, 2.5 V, or 1.8 V. Each output bank has its own V_DDOX supply, supporting 3.3 V, 2.5 V, or 1.8 V.
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Rev. 1.0