SI53306 Datasheet, PDF (13/29 Pages) Silicon Laboratories – 1:4 LOW-JITTER UNIVERSAL BUFFER/LEVEL TRANSLATOR

Si53306
2.2. Input Bias Resistors
Internal bias resistors ensure a differential output low condition in the event that the clock inputs are not connected.
The non-inverting input is biased with a 18.75 k pull-down to GND and a 75 k pull-up to V_DD. The inverting input
is biased with a 75 k pull-up to V_DD.
VDD
RPU
RPU
+
RPD
–
RPU = 75 k
RPD = 18.75 k
CLK0 or
CLK1
Figure 5. Input Bias Resistors
2.3. Universal, Any-Format Output Buffer
The Si53306 has highly flexible output drivers that support a wide range of clock signal formats, including LVPECL,
low power LVPECL, LVDS, CML, HCSL, and LVCMOS. SFOUT1 and SFOUT0 are 3-level inputs that can be pin-
strapped to select the output clock signal formats. This feature enables the device to be used for format translation
in addition to clock distribution, minimizing the number of unique buffer part numbers required in a typical
application and simplifying design reuse. For EMI reduction applications, four LVCMOS drive strength options are
available for each V_DDO setting.
Table 17. Output Signal Format Selection
SFOUT1
Open*
SFOUT0
Open*
V_DDOX = 3.3 V
LVPECL
V_DDOX = 2.5 V
LVPECL
V_DDOX = 1.8 V
N/A
0
0
LVDS
LVDS
LVDS
0
1
LVCMOS, 24 mA drive LVCMOS, 18 mA drive
LVCMOS, 12 mA drive
1
0
LVCMOS, 18 mA drive LVCMOS, 12 mA drive
LVCMOS, 9 mA drive
1
1
LVCMOS, 12 mA drive LVCMOS, 9 mA drive
LVCMOS, 6 mA drive
Open*
0
LVCMOS, 6 mA drive LVCMOS, 4 mA drive
LVCMOS, 2 mA drive
Open*
1
LVPECL low power
LVPECL low power
N/A
0
Open*
CML
CML
CML
1
Open*
HCSL
N/A
N/A
*Note: SFOUTx are 3-level input pins. Tie low for “0” setting. Tie high for “1” setting. When left open, the pin floats to V_DD/2.
Rev. 1.0
13