SI53306 Datasheet, PDF (17/29 Pages) Silicon Laboratories – 1:4 LOW-JITTER UNIVERSAL BUFFER/LEVEL TRANSLATOR

Si533xx
CMOS Driver
Zout
Rs
Zo
50
CMOS
Receivers
Si53306
Figure 8. LVCMOS Output Termination
Table 19. Recommended LVCMOS R_S Series Termination
SFOUT1
SFOUT0
3.3 V
R_S (ohms)
2.5 V
1.8 V
0
1
33
33
33
1
0
33
33
33
1
1
33
33
0
Open
0
0
0
0
2.7.1. LVCMOS Output Termination To Support 1.5V and 1.2V
LVCMOS clock outputs are natively supported at 1.8, 2.5, and 3.3V. However, 1.2V and 1.5V LVCMOS clock
outputs can be supported via a simple resistor divider network that will translate the buffer’s 1.8V output to a lower
voltage as shown in Figure 9 below.
V_DDOx= 1.8V
R₁
LVCMOS
R₁
50
R₂
1.5V LVCMOS: R₁ = 43 ohms, R₂ = 300 ohms, I_OUT = 12mA
1.2V LVCMOS: R₁ = 58 ohms, R₂ = 150 ohms, I_OUT = 12mA
50
R₂
Figure 9. 1.5V and 1.2V LVCMOS Low-Voltage Output Termination
Rev. 1.0
17